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The process of attaching a component to your package substrate involves many factors, including heat. What happens whenever heat is applied to something? Expansion, of course! How much your die expands during the assembly process will be influenced by many factors, from the material composition of both die and substrate to the temperature extremes encountered during their melding. Your package layout tool cannot tell you what these values are; however, it IS perfectly positioned to convert the values you provide into adjustments to the landing pad patterns on the substrate surface.
In the Cadence® SiP tool, with its fully-integrated symbol editing environment, application of thermal expansion coefficients to individual mounted component allows you the flexibility to account for material differences. Conveniently, recording the values onto the components frees you of the need to remember them yourself. Let's see how things all come together by first looking at the command and then applying it to a simple example die. You may just be surprised at the impacts the expansion process has.
Select any of your components while in the SiP Symbol Edit application mode, and you’ll discover the CTE compensation entry in the right mouse menu’s listing of available actions. CTE is short for Coefficient of Thermal Expansion. Using the full text everywhere would be too long in a menu. It's more than I want to type every time in this blog! Selecting the command presents you with an options tab that looks initially like the image captured below:
Don’t let the small number of fields dissuade you! These capture all the options you need to manage your thermal adjustments – though if they prove not to, we encourage you to get in touch with the team, either by leaving feedback here or contacting your Application Engineer, so that we may work with you to extend the tool.
Expansion is always applied from the center of your component, regardless of where the symbol origin is defined. And, by providing separate ratios for X- and Y-axis expansion, you have the flexibility to handle different component width and height values. The more accurate the values you get from your experts, the better the landing targets will be arrayed in the layout. The better the targets, the better the durability of your final substrate.
We provide you the option to create a new, derived symbol definition. This is so that you may preserve the original, unmodified symbol. At any time, you can use the ALT_SYMBOL functionality within SiP to return to the original. The original symbol definition may be used as a starting point for running checks with different values. You should always plan to go back to the original symbol definition, which represents the part as you were provided by the IC designer. Doing this will ensure that you don't introduce progressive rounding errors. With every adjustment applied (because the placement grid for tools is not infinitely accurate), some rounding of coordinates naturally occurs.
The ghost pins, configured at the bottom of the form, complement the original symbol definition. They are shapes on the specified non-conductor layer which show where the original pins were, without having to place an instance of the original definition into the design that isn't there on the final substrate. You can reference this layer visually in the display, but also in PDF and other documentation outputs if you need the reference for discussions among your team or with the IC designers.
A picture is worth a thousand words, as the saying goes. Above, the green pads represent the pre-expansion pad locations (or the “ghost pins”), while the pink pads show the final positions of the post-expansion pads. Having both visible on-screen gives a great visual before-and-after comparison. I used different values for the X- and Y-axis expansion to show you the impact that can arise. You should be able to see that the top and bottom pads almost touch the original green ghost pins, while those on the left and right have a clear separation.
Change is inevitable. What happens when you receive a new version of the die, whether that comes to you as a die text file or an XDA die abstract, from your IC design team? This is when having all the values recorded in the design is of the utmost use. Optical shrink values can be reapplied to the die, then the recorded CTE values will automatically be reapplied as well. The die replace tool will then stretch your substrate routing and bond wires to the new pad locations to maintain connectivity.
Allow your Cadence layout tool to manage the impacts of all those changes for you, so that your time is spent assessing potential concerns and communicating those back to the chip designers. The faster you can provide chip designers with that information, the more time you all have to make the ideal changes to the proper substrate to ensure top-performing designs with maximum yield. As a team, working together, you can close on your completed design from a chip, through the package, to board faster and more accurately than ever before.