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When you are placing components (or defining your BGA pattern), often it is necessary to escape each of those pins to a given internal layer. This could be to get your power and ground supply to the designated plane layer. Or, it might be the first step in the routing for your signals, if you know which layer(s) are the primary layers for designated nets.
In any case, the pins themselves for a flip-chip die are surface (or cavity) mounted. That is, the component is affixed to the designated landing pads on the target layer. Knowing this, it is a wise idea not to try and include internal layers inside the pin padstack itself for a few reasons:
When you place the die in packages with different stack-ups or layer counts, different escape structures will likely be needed,
If the chip is mounted on another die or interposer in a stack configuration, those layer transitions will, again, necessarily be different,
You will not get an accurate count of the vias in the package layers, as the transitions incorporated into the padstacks for the pins won’t be counted,
… and so on. I’m sure you could give me more reasons than I could give you!
What, then, is the alternative? Are there better methods for defining the escapes for pins without incorporating everything into the padstack definition for the pins directly? With the latest 17.4 ISRs of Allegro Package Designer Plus, there are! Continue reading for an overview of this just-released technology to understand why this might be just the thing you need in your next design start.
When you install ISR 11 of 17.4 and have the Silicon Layout option package, you’ll find the Import GDS Structures menu item under SI Layout. This new command, interface shown below, is freshly released and continuing to evolve based on your collective feedback.
The idea here is to encapsulate the entire escape structure for your pin in a single stream file. The stream format is highly stable and supported by every EDA design tool out there, meaning you can use these same structures not just in Allegro Package Designer, but in Virtuoso, Innovus, or any other tool and get the exact same geometries. Additionally, being GDSII, you can validate your construct in the Cadence Pegasus sign-off tool to know that it abides by all your manufacturing partner’s requirements before you ever even apply it in your design.
Depending on your manufacturing partners and their level of involvement with your design, they may be able to provide or work with you to develop, these structures for this and future layouts. Lessons learned today can be applied to the designs of tomorrow.
Important items here to take note of include that you can (with a single run) import a complete set of structures for your design. All you need to change is the layer conversion file to match the cross-section for your active layout. Then, import all your padstacks to add the vias, pin padstacks, and (of course) built-up routing structures to be used for your pin extensions.
The tool can automatically extra the single-layer pads from the GDSII cells to be used as your pin padstacks for the die and BGA components. The remaining via padstacks (if you want, and I recommend this option in particular!) can be automatically applied to your constraint set via lists, ready to use without any additional action on your part. Time (and mouse click) savings are a great thing!
When the tool extracts (or identifies your own) pin padstacks within the structure, the padstack definitions get an association with the routing structures that contain the vias, clines, and shapes that collectively define the extension down to the routing layer.
Here, we see a GDSII rendering of a simple structure with the cell hierarchy for the via padstack definitions and the pin padstack to be used on the top-level – though, obviously, with the simple selection of an alternate layer conversion file, you can completely remap this to different layers. Below that, the same structure after import to the design and use for a die pin:
Because of this, whenever that padstack is referenced for a pin of a component, the extension elements are added to it. Not only are they added, but they are also “locked” to the pin, meaning you cannot accidentally move them to be misaligned from the intended pin position. This is similar to how fillets on pads work today – you can query them in the show element, you can see them and connect to them, but you cannot pick them up and move them by themselves. Instead, to move them, you must move the owning pin (or the pin’s component) to a new location.
Moving or deleting the entire component? All the extension elements on the pins go along for the ride. You don’t need even to select them. Picking up the component/pin is itself enough to have the structure move.
Add a pin through the symbol edit application mode, swap the padstack on a pin with replace padstack, or any other action you can think of will seamlessly apply the necessary structure manipulation for you.
These structures do NOT need to be defined for a single net only. As with the high-speed routing structures you are already familiar with, the hierarchical nature of the GDSII format can be used to define surrounding objects (usually shielding ground net elements) around the pin and its vias.
A single text label (G1) on each branch of items identifies usage for future net mapping
The possibilities are nearly endless. Should you be concerned about defining multiple extension elements for different pins that have, inside of them, the same via padstack definition – fear not! The cell name defining the via in the GDSII file is used as the padstack name.
You can read in GDS-based escape structures and export them to XML in the standard format for structures if you want to (and vice versa). The ability to view and dynamically remap layers – or exclude certain layers – through the change of conversion files can be a handy little trick.
When you bring in a set of structures all using the same cell name for the padstacks, the import process will identify this and reuse the pad definitions for each of the structures. One caution, though: Each macro should have its own pin padstack definition name. Why? Because, as you might have surmised, since the pin padstack gets the extension structure associated with it, linking more than one would break the ability for the tool to know which one you want to be used, automatically; for that reason, it is not supported (today).
As this new flow develops, we are actively seeking your feedback and ideas. How do you see applying these structural elements to your designs? Are there additional objects which you would incorporate into the structure to drive other requirements in your layouts?
Let us know, by reaching out to your Cadence support experts. Your suggestions help us continue to develop the most full-featured IC package layout tool out there so that you can get your designs completed on time, on budget, and in the hands of your customers! Download new ISRs (and releases) as they come out to follow along with the enhancement of this new concept!