Get email delivery of the Cadence blog featured here
With increasing design complexity comes the need to create test vehicles to qualify new processes and ensure that the substrates will be able to tolerate the expected wear and tear, long term load, and other situations that may not fall under the umbrella of “ideal conditions.”
To that end, creating a daisy chain version of your substrate that can be used for reliability testing purposes is becoming a standard task for more designs and designers. But, how do you create these designs quickly and efficiently?
With the latest SiP Layout tools, everything you need is just a few clicks of the mouse away. From creating the 2-pin nets to tie connections together to establishing the basic—or complex—sequencing of the daisy chain connections and adding the routing connections between the pin pairs, the process is quick, easy, and relatively painless.
To learn more, keep reading as we walk you through an exciting new beta feature in the June 2015 update release of SiP Layout XL—the Daisy Chain command.
So, you have a design that you need to create the daisy chain connections for. What is your first step? To begin, all you need is the completed substrate—or, at least, completed to the point that you are ready to create your daisy chain from. Let’s presume you are doing a daisy chain for your flip-chip die component.
Before you create the daisy chain assignments, you will want to remove the routing from the flip-chip pads on the substrate. After all, you’re trying to route the daisy chain connections, and these will get in the way. Remove them with the delete, cline change width tool in delete mode, or your favorite cline-deleting tool, trimming back to the edge of the die component or as far into the substrate as you need to. Be sure to remove any via pads and shapes in that region as well, so that they don’t get in your way.
Next stop, run the Route -> Daisy Chain command (If you’ve not already enabled it, do so in the User Preferences form by enabling the “icp_daisy_chain_beta” variable and restarting your SiP session). This will give you a simple, yet very powerful, set of options in the options panel, which look like the image below:
Here you can see you have options for how to generate the pin pair nets and what to use for their net names. In addition to that, you have controls for how to pair pins together, and how many pins are between pairs, as well. Finally, you have the option to add clines to connect the paired pins together as the tool is processing your design. There’s also the staggered pattern option, but let’s hold off on that for just a minute.
In most situations, you’ll want the system to create the nets for you, and probably want to create the clines as well. But how do you determine the direction that the pins are paired in? You’ll find you have a few options, here. There are the typical horizontal and vertical directions, but there is also an additional option, which will follow the sequencing of the pin numbers on your component. Don’t ignore the power of this option.
When following the pin numbers, you can use the symbol editing application mode to number the pins in any order that you want automatically. It has an abundance of numbering styles from spirals in the clockwise and counter-clockwise directions, to completely custom patterns where you can number pins by dragging your mouse over the pins to re-sequence their numbers. This gives you full control over both the numbering and the daisy chain pattern, and it also lets you export a ball map showing things in a spreadsheet format you can bring into your documentation package.
Don’t worry if you don’t want to renumber your pins. You can always process sets of pins with different settings by turning pins instead of symbols on in your find filter with the daisy chain tool. Options to allow you to design things your way are always to be found in the Cadence IC Package layout tools!
You caught me. Why would you need, or want, this option? As you know, the substrate pin connections are only half of the daisy chain pattern. There’s the pattern on the die side, as well. Wouldn’t you like to create that at the same time, and in the same window, so you can verify there are no open links in your daisy chain sequence?
With this option, you can. Generate your daisy chain for the substrate landing pads of your flip-chip. Then, using either a second copy of the die on a different layer or, if you’re lucky enough to have a co-design die, by showing the IC details representing the die component itself, generate the daisy chain for the other side of the connections.
Running the second pass in start staggered mode will give you an elegant pattern that connects pads 1 and 2 on the substrate, then 2 and 3 on the die, and back to the substrate to go from pin 3 to 4. If you’re following your pin number ordering, you can create a perfect pattern of connections from the first to last pin with complete confidence that the chain is unbroken and doesn’t miss a single pin on the component.
What you’ll get might look much like the image below, if you’re using a spiral pattern (we’ve only showed the upper-left corner of the design to keep things at a reasonable zoom level). You can see the connections in blue on one side of the interface and green on the other.
Hopefully, you’re downloading the latest 16.6 ISR of SiP Layout now if you’re an engineer responsible for daisy chain creation. You’ll be getting started in no time at all.
But, no tool is perfect. What other options do you need to set up your daisy chain with the minimum effort but maximum accuracy? Contact your Cadence support representative today with your ideas. We’d love to hear from you on how to make the tools even better!