Get email delivery of the Cadence blog featured here
They say Moore's law is slowing. It may be slowing but it is still running - it has not stopped! And, it has been running at full throttle for quite a few decades now. The net result of this run? Well, you can't design ICs in isolation from the package. The need is very basic, very down-to-earth; your schedules are tight and you want to address any issues at the earliest.
You can't wait. If you are a package designer, you will like to see the die in its proposed package in an early feasibility state so that you can change the die pin layout before the final IC design. If you are an IC designer and know the packaging requirements and how the arrangement of the pins affect the package design, you can minimize package costs. By looking at the Virtual System Interconnect (VSIC) model for the chip and package together early in a co-design process, you can rule out earlier design options that cannot meet the electrical or high-speed signal integrity constraints. That means a faster time to market for the entire project. At the same time, you need to consider the floor plan and I/O placements inside the IC. When the feasibility phase ends and the project enters the design stage, you can use the information from the preliminary feasibility as a reference or for seeding the production design of both the IC and package.
What you need then is the layout and IC tool to work together to support co-design to minimize the cost of production while ensuring that the die and package combination meet all design requirements. For example, if you are using Innovus® Implementation System to design your ICs and Allegro® Package Designer Plus to package these ICs, you will want a flow that eases and enables co-design. And, that's what you will see happening in this post.
Before starting with steps, you must know about the die abstract file (XDA) that is at the core of the co-design business. The die abstract file is used to exchange information between chip design and package layout. It is an XML file containing die size, pin/bump location, and connectivity or IC net names at the pins/bumps. It can contain other information, such as RDL routes and macro boundaries. Now that the die abstract file is known, it's time to start with the steps.
This one is quite simple actually, write the die abstract file from your IC application. From Innovus Implementation System, use the write_codesign_die_abstract command to generate the die abstract file.
The first thing you do is copy the die abstract file generated in step #1 to where the package database (.mcm) is located.
Open the package in Allegro Package Designer Plus and choose Add – Co-Design Die. Browse to the .xda file and then use the Place Co-design Die form to place the die. That places the die - that simple. Of course, you can choose to promote and assign the IC net names to the bumps in the package netlist. You can also specify die attachment, location, rotation, shrink, and scribe width.
Then, if you need to change the padstack of the bump pins to match the IC, do that in the Symbol Edit application mode.
Here, you come to the core of the packaging activities. Start by adding a package using one of the options from Add – Standard Package.
Modify the package net assignment. Exporting a spreadsheet is a smart way to modify BGA and die nets. You can then import the changed spreadsheet to update the package design. Tyler Lockman explains the power of this method in A Classic Revisited - Ball Map Spreadsheets. You can also use the Assign Net option of the Logic menu to further modify package net assignments.
You will now want to optimize the connectivity between the co-design die and the package but you will also want to let the IC designer see the package ball arrangement. So, go ahead and export a package overlay file. Again, an XML file that can be read by Innovus.
You might also want to move the bumps around a bit to fine-tune the design. Go ahead and do that too.
Finally, when done, export a die abstract file because you want the bump pattern changes to propagate to Innovus.
Now is the time for you if you are the IC designer. It's your turn to copy the .xda file and read it into Innovus. Use the read_codesign_die_abstract command for that. And while you are at it, read the package overlay file too to see the package ball arrangement. You will definitely modify the design, say, swap bumps. But once you are done with your changes, do not forget to pass on the changes to the package designer. So, go ahead and write a new die abstract file and share it with the package designer.
That puts the ball back with the package designer again. So, now it's your turn to bring in the changes made by the IC designer. But that's easy with the Refresh Co-design Die popup option in the Symbol Edit application mode. Check the connectivity details and make any modifications required. But before doing that, it will be a good idea to run the Die Abstract Compare (Reports – Die Abstract Compare) utility to see the differences in the original and the ECO die abstract files.
And, that completes the journey of the die abstract file and ensures the IC and packaging are in sync as they are being designed.
Do you want to try out the steps? Delve deeper into the details of each step? Well, you can try out all the steps right away with a sample design using the IC-Driven Single Package – Single-Die Flow with Co-design Cockpit Rapid Adoption kit available at Cadence® Online Support if you are a Cadence customer with a valid login ID. The RAK sample comes with the Co-Design Cockpit that makes the steps even easier. The Co-design Cockpit is used to facilitate the co-design creation and connectivity initialization in the package design.