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Recently, an article was published in Chip Scale Review by Cadence product manager Kevin Rinebold talking about maximizing the value of silicon interposer technology using system planning (see page 30). Today’s semiconductor technologies help meet the challenges of developing electronic products that are smaller, more efficient, lower cost, use less power, and in less time to the market. Achieving these objectives requires technology tradeoff and compromise.
With the ongoing discussion of 3D-IC and the promise of a higher level of integration, smaller form factor, and a faster design cycle, it also brings additional thermal, timing, and power management challenges. As companies evaluate the trade-offs of power, performance cost, and time to market, many are choosing to adopt “2.5D” technology.
2.5D IC/SiP using a silicon interposer and TSVs
However, 2.5D technology also brings new challenges to the industry. One of them is silicon interposer, which is used to provide higher density interconnection. While much discussion in the industry is around TSV construction, how to optimize the whole system -- including the silicon interposer -- to get the best performance with the lowest cost needs serious consideration.
If the die and package are not considered when implementing a silicon interposer, the chip-interposer and interposer-package connectivity can adversely impact performance and add cost to the overall system. That’s why considering silicon interposer as a part of the overall system in the context of chip, package and board is crucial for the 2.5D design. A comprehensive system view and connectivity optimization can reduce the number of signal crossovers in the overall system. The interposer can be validated against design specifications through route feasibility in conjunction with system signal integrity and power integrity analysis. In the end, the optimized silicon interposer can be passed to IC implementation tools for final routing and manufacturing preparation.
There are several aspects that need to be considered when performing system planning among chip, interposer, package and board, which set several requirements to the system planning environment. In this article, Kevin discussed a couple of major requirements for system planning environment.
Most importantly, system planning environment should contain system hierarchy and data management capability, which will allow users to use data of various sources and formats; as well as the ability to simultaneously manage and interact with multiple designs across the die, package, interposer and board. Comprehensive system planning also requires co-analysis capabilities to support power, signal and emissions design. To read the full article, please see page 30 of this issue of Chip Scale Review here.