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Molding caps aren’t something we talk about too frequently around here. We all know they exist, and they serve an important purpose, of protecting the delicate die from potentially harsh environmental conditions. They impact how well heat can be dissipated from the chip, too. Why, then, don’t we spend much time focusing on them?
It’s a good question. I could hypothesize as to the reasons, but that’s not my forte. Instead, let’s focus on what the Cadence® Allegro® Package Designer Plus tool allows you to do with caps. From there, maybe we can, working as a group, determine the next steps here to take them from a last consideration to a design element that’s present from start to finish, ensuring that the assembled physical package is the very best that it can be.
If you do nothing else in the tool today, Allegro® Package Designer will assume that the molding cap is the same dimensions as the package’s outline. When you first define your BGA (which includes the outline, since, well, it IS the substrate for most packages!), you’ll find that the molding cap is now able to be seen and displayed in the 3D Viewer. More on that in a bit.
Take our very simple design, shown below. It has a JEDEC BGA with a single wire-bonded die in the center. A few power/ground rings complete things for a referencing perspective.
Subsequently, if you bring up the 3D Viewer command, you will need to enable the display of the cap and assign it a height above the top layer of the substrate. This is necessary because the cap doesn’t exist on a substrate layer in the cross-section. It is not, after all, a part OF the substrate layers. At least, not directly.
Below, I have enabled display of the molding cap and assigned it a height of 200um. I have also enabled the display of the soldermask layer (50um) and the drawing of the dielectrics. Turning the dielectrics on has no impact on the overall height or relative placement of objects. It does, however, give an easier sense of what we are looking at.
From a skewed top-down view of the package, it is difficult to make out the molding cap. If it were drawn opaque, you wouldn’t be able to see inside of the package. As that is not terribly useful to you, the package designer, it is given a gray coloring with high transparency.
Looking from the side, however, things become much clearer. It is easy to see “through” the molding cap to the die and its wire bonds inside. Below are the dielectrics and other layers that collectively form the package’s substrate layers. At the bottom are the BGA balls in red, completing the picture.
This is good for simple modeling of the package. It’s more accurate than not seeing the cap at all. Beyond that, you see the basic relationship between all the (stacked) dies and bond wires in the design. If, in the above image, the wires stuck up through the light gray of the cap… you’ve got a problem.
Basic outlines are well and good but rarely do they meet the requirements for an accurate system. If you need an outline more than simply tied to the design outline shape, Allegro has you covered. Define a PACKAGE_CAP layer in the SUBSTRATE GEOMETRY class, shown below:
On this layer, you can define all the shapes which represent caps in your package. You may have a single cap over one stack of dies in the center, with a separate cap on some resistors in a corner of the BGA. Whatever your arrangement is, simply defined the outlines on this layer. Below, I’ve created a (very unrealistic, I admit) circular cap on top of my bonded die, plus two random square caps in the top left and right corners:
Today, all caps will have the same height, as defined earlier in the 3D Viewer setup form. When we look at the above in 3D, then, we see this:
You can play around with getting things correct to the manufactured design, leveraging the 3D view to ensure clearances meet required tolerances. When you’re happy, you can turn off the PACKAGE _CAP subclass in the layout window, unless you need to make further changes.
We closed over it, briefly, earlier. A molding cap is meant to protect the die and bond wires from environmental effects. That purpose is… somewhat compromised… if the cap will crush the bond wires or dies when it is mounted onto the completed package.
The 3D Viewer, though, helps you with that. Define a 3D DRC rule to check spacing between the cap and the wires. You can see how I have configured this below, as well as some of the resulting violations. To make it clearer, I turned the cap from mostly translucent to an opaque black. Where the wires rise through the black, they are rising ABOVE where the top of the cap sits after mounting!
Seeing this here provides immediate feedback to you, as the designer, that something is amiss. Either your bond wire profiles need to change (perhaps using a reverse bond profile will get you low enough to stay under the cap?) or you will need a taller cap.
The trade-offs here may be costly. A taller package may not fit in that ultra-thin cell phone, but will a lower bond wire profile increase the per-unit unit cost of the package itself? Those, my good friend, are choices I leave for you to make.
We’ve looked at how the cap can be defined in the 2.5D layout database today, and how that can be extrapolated, rendered, and validated in the 3D landscape. What else do you consider with your cap that we haven’t talked about – what would add more value to your design flow?
Do you need greater detail for describing the sides of the cap? If the sides are not vertical today, but instead are sloped, would having the detailed profile of each side of the cap have a meaningful impact on your thermal analysis results? What about mechanical / board outline symbols with associated STEP modules for describing the cap collected in your part library? Do you want to associate a cap with each die stack in your design?
From a non-physical geometry stance, describing the gas or other material contained under the cap and surrounding the die and bond wires may be more influential. Then, having this feed-forward to the Celsius tool for thermal analysis ensures that the layout and analysis tools remain synchronized at all times.
Allegro Package Designer Plus offers the ability to generate a library part through the File – Export – Board Level Component command that can then be placed onto a package or atop another IC package in a package-on-package setup. It could be most interesting to you to have that export flow include a STEP model (including the detailed molding cap profile) such that downstream assembly and manufacturing rules are more easily checked.
Whatever your need, reach out to our customer support and marketing experts to share your ideas. We love to hear them and incorporate as many as possible into future versions of the tool!