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I think every traditional package designer understands what a plating bar is and the purpose it serves. There to provide electric current during the manufacturing process, each net is connected out to the perimeter of the BGA, which allows for the current to reach all the areas to be plated.
The plating bar itself is normally described as a metal connection around the outer edge of the design. It will extend slightly beyond the final BGA outline. By connecting all the pins together out here, when the BGA itself is separated from its neighbors, the plating bar is removed. No shorted nets remain – unless you are using an etch-back process and will remove shorts between nets internal to the BGA outline; this is an extra step in the process.
For the Cadence Allegro Package Designer tools, the plating bar is composed of two pieces. First, the “bar” itself (the conductor ring around the outside) is offset from the package edge and shorts everyone together. Second, pins of the plating bar component are created for each routed net where it attaches to the plating bar.
If any pin isn’t connected to the plating bar, or if a net isn’t represented by one or more pins on the bar component, then you know something is wrong.
This is a fairly simple process and procedure. With new design styles like silicon interposers and system on wafer designs, the traces exiting the edges of the substrate boundary horizontally instead of vertically through a ball, may not be tied to a plating bar at all. Instead, they may connect to another neighboring instance in a larger pattern.
With these designs, then, where a net exits (what layer, what side of the package, even the XY location of the end) is critical. If the traces do not exit aligned with where its mated connection does in the next instance, then the entire design will fail to function properly.
Additionally, these edge-to-edge connections need to be in your netlist to make sure nothing is missed. It makes the mapping of the interfaces easy to manage, too. A plating bar component is not appropriate for this type of real connection.
Edge Connectors are the component object in Allegro Package Designer used to create and work with these interfaces. These can be made through the SI Layout menu’s (Silicon Layout option required) Create Package Edge Connector tool, shown below:
When launched, if you take only a cursor glance, you may think you have run the plating bar create tool. This is because of the similar physical geometries that are required in both cases.
Closer inspection will reveal critical differences. First, be sure to name your component. The edge connector is an IO class component, like your BGA. It provides IO to neighbors instead of the next level of the substrate. Therefore, the reference designator, device name, and symbol name are all much more relevant than with a plating bar.
What advantages does the edge connector component provide? If you reuse the edge connector’s interfaces in the next instance, you will know that the routing aligns before you ever compile the complete, multi-instance substrate in a single database.
Let’s use a simple example. If I have one instance which is a smaller block of a 10 x 10 instance larger design, then I want the north side of one instance to exactly match up with the south side of the abutting cell. Same with the east and west.
With the edge connector tool, first, route one side of the design. Let’s say the east. When the routing is complete, generate the edge connector. Then, using the symbol edit application mode, grab these east-edge pins. Copy them to the west edge, using one of the corners of the substrate as the reference point, and you’ll be certain that the two sides of adjacent instances will be aligned perfectly.
At this point, the only real step remaining is to assign the correct nets to the west edge connector pins. This will give you up-front feedback to some questions which require answers as early as possible:
Do I need to swap any pins of the die interface to get associated nets routed without needing to change layers unnecessarily?
Are all differential pairs and buses ordered ideally?
Should nets going to BGA balls under the die, not to adjacent cells, be relocated to stay out of the way of the longer, same-layer routes?
For all nets, are the correct sets leaving out the correct side relative to the top-level netlist?
Knowing these answers now will give you confidence that the solution will work. If it does not, corrections may be made most effectively early in the design flow. Unless you like doing something twice – I don’t know any of us who has that kind of free time, though!
After the initial interface design, if any changes need to be made, you will be aware of their impact on the surrounding module instances. Pins cannot be moved except through the symbol edit application mode or UNFIXED_PINS property. There is no change that one designer will slide or shove a trace without realizing it. The endpoints of the routing is locked.
If you feel that this doesn’t give you enough benefit for your flow (maybe you already have the desired interface points), consider your routing duties. A router, as we are aware, needs to have both a start AND an endpoint for the connections.
The package edge connector’s pins provide these endpoints. You can run an auto-router, any of the interactive or auto-interactive routing tools, or your own algorithms to run the routes. If they get to the edge connector pin successfully, again, you know they are right.
Finally, since you know where the endpoint is in both modules, you can make calculations for total propagation delay, relative prop delay, etc. As you tighten up and complete the routing in one instance, you can take those results and use them to update the allowable delays and tolerances in the next. Balance where you add and delay and phase tuning to ideal locations (maybe you need some on the east side of this instance and others on the west side of the next in order to fit everything in).
Great question! If you are, indeed, making a 10x10 array of these modules, why not simply place all hundred dies into the same instance and route them together? I could share many reasons with you, but I will give you the top ones for me. Feel free to add your own:
Faster validation of changes. Since you know each instance is identical, you need not run checks on the entire wafer map. Run a single instance, instead, and know you’ve caught 95% or more of the violations,
If I have a DRC violation in one instance, correcting it there corrects all 100 cells. I only need to fix a problem one time,
When the next iteration of the design starts and I need a 20x20 array, no work needs to be done. Just define a larger matrix of your existing instance,
Less names to worry about in the design, less instances to refresh on an ECO. Less… everything (except productivity), really.
Many tools, like the Cadence Virtuoso platform, can define a matrix of cells. If you turn your instance here into an OpenAccess cell layout then step-and-repeat it to create the completed large design, it can use a hierarchy for the GDSII data and other areas to create a smaller design with increased hierarchy.
I hope the brief introduction to edge connectors, available today in the SPB 17.4 release of Allegro Package Designer Plus, will give you ideas on how to improve your performance while saving you manual work!