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The task of IC/package co-design causes multiple challenges during the design cycle and one of them is to update the netlist of co-design die or BGA in the middle of the design cycle. The current process of updating connectivity provides no flexibility for selective updates because the process modifies the design connectivity in one go after importing the revised die or BGA text files. Also, the current process is time-consuming, error-prone, and difficult to review. Netlist updates from partially-routed packages, with partially-routed connect lines that can have incorrect connectivity from the shapes they touch, make this process even more complex.
In release 17.4-2019, HotFix 013, a new command push connectivity has been added to Allegro® Package Designer to address the above challenges. In this post, I will talk about the usage of this command at length. First, let’s take a look at the design flow steps followed when modifying the design connectivity using this command:
Import the latest die text file using Add ─ Standard die ─ Die Text-In Wizard to update the die symbol and its netlist. Ensure the Run derive assignment on exit option is disabled. Otherwise, it will allow the updated connectivity changes to propagate to the rest of the design.
The following sample design illustrates a flip-chip design, which has a few pins routed to the package pins. The connection traverse multiple signal and plane layers.
After importing the die text file, the connectivity to the die is updated but not pushed to the other connected objects, such as clines, vias, and BGA pins. Hence, DRCs are created at the die pin after the import as you can see in the next image.
Reviewing the updates to the design after the import of the die/BGA text file is necessary. You should verify the location of die pins and the modified pin-to-net connection. After reviewing, use the command to push the connectivity to all the objects that are physically connected to the die pins. The command pushes the new connectivity to all the physically connected objects except dynamic shapes and filled rectangles. If the command finds a dynamic shape or filled rectangles as connected physical objects, the connectivity update stops before these objects. This is done to prevent incorrect connectivity updates to the thousands of objects that are connected to dynamic shapes.
Now, let’s see the different ways of using the command and how effective, easy, and productive this can be.
The Push Connectivity command provides a lot of flexibility by enabling different courses of action while modifying design connectivity. To run the command, choose Logic ─ Push Connectivity.
When the command is active, the Find filter and the Options tab displays relevant options, as shown in the following image:
The command offers multiple ways of selection to drive the connectivity changes. I am listing some alternatives:
Once the command is completed, you can open the log file to review the status for every object type and the associated connectivity changes.
If you have selected the Run purge unused nets on exit option, the Purge Unused Nets dialog appears when you choose Done from the pop-up menu to exit the command. This dialog lists all the unused nets. You can choose all or selective nets to be deleted from the design after command execution.
Your design has now been updated and has the latest connectivity. As you can see in the following image, connectivity is pushed to all physically connected objects from die pins to the BGA ball. All the DRCs are gone from the die pins, which were shown earlier when you had imported the die text file.
The push connectivity operation provides a very dynamic, flexible, and productive way to do connectivity updates for different package designs. This flow helps the IC Package designers immensely to control the design connectivity without impacting the integrity of the design.