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Those who work in the IC Packaging design space have some unique challenges. We bridge between the IC design world (90/45-degree traces with rectangular and octagonal pins) and the PCB domain (any-angle routing, filled planes, and a multitude of pad shapes).
Because of this, and dependent upon whose side of that tug-o-war we are closest to, the connectivity modeling of the database may need to change. In the Allegro® PCB design tools, connectivity to a pin or via means you must get all the way to the origin point of the padstack. But in the IC space, any amount of metal overlap between the two design elements is considered a connection.
Neither model is inherently more “right” than the other. Manufacturing tolerances, alignment variations, even the vectorization of arcs into straight line segments can lead to small variations in the final metal for a layer. When dealing with primarily orthogonal connections, this is mitigated and easier to manage, while with arc routing and shape clearances around circular pads, the accuracy of intersection points becomes fuzzier.
Why are we talking about this, though? Simply put, the Allegro Package Designer Plus tool allows you to tweak its connectivity engine in certain areas to better align with the variations we just described. Read on to learn about the defaults and how to change them in your next design.
By default, the Allegro Package Designer tool uses a connectivity model that is heavily biased towards the PCB flow above. That means that any connection to a pin or via needs to go to the pad origin. All connect lines have rounded end caps on them (and rounded outer corners of vertices along the trace path).
The main exception to this rule is in the objects rarely encountered on a board layout – bond wires. Wires can connect anywhere on either bond fingers or die pads if they touch down on the pad itself. Rules are available in the wire bond environment to ensure you stay far enough inside the edge of the pad / soldermask opening not to have manufacturing issues.
Why are bond wires treated differently, you ask? Because they are the lone 3D connection element in the design (Let’s not count a via, please. They are purely vertical). A wire follows a curvature through 3D space. It is subject to bending and warpage as the refill material is injected. In short, it’s not the same as a trace routed on the substrate itself. For that reason, it needs special abilities to allow it to connect where it needs to and to accurately reflect its physical geometry.
In the example above, none of the wires shown connect to the finger’s origin. One is near the inside edge, minimizing its length; the second, at the outer edge to maximize it; the pair connecting to the last finger are offset evenly to meet spacing requirements so that the capillary of the bonding machine doesn’t break one wire when adding the second.
In most cases, connecting a trace to the center of the pin or via is neither difficult nor unexpected. The drill holes for the via is, most commonly, in the middle of the pad. Thus, the signal traveling along the path MUST get to the center for it to move through the plated drill hole to the next layer. The length of the cline defines the total horizontal length on that layer, and the via contributes only the vertical distance between the layers.
Shapes are a different matter. If a shape overlaps a pin or via, the metal of the two completes the connection. The horizontal path length is less well defined (especially if the shape is degassed or has many irregular patterned voids in it!). The connection is still well-defined.
In the PCB design flow, shape and pad use the same connection requirements as cline and pad. You can, however, change this. Add the PAD_SHAPE_TOUCH_CONNECTIONS property at the drawing level of your database, shown below:
Once done, if the shape and pad overlap at all, then they are considered connected. This is best shown by the lack of ratsnest lines, or a simple query in show element. You can also visually tell by the clear difference in the voiding done by the dynamic shape.
If a dynamic shape can’t connect to the pad center, normally it will void to the pad and instead use thermal ties (if possible) to form the connection. With touch connections configured, the two will directly connect, which has the side effect of meaning the shape does NOT need to void to the pad. This can make connecting the shape to the pads easier.
It is VERY IMPORTANT to note that, in this mode (like an IC design flow), and level of overlap is enough to establish a connection. Because of this, we strongly recommend using the Define Variants tool, under the Manufacturing menu, to generate the min and max tolerance views of the design. These will show you clearly whether there is risk of a broken connection when the manufacturing process is off from the nominal, or ideal.
Situations like the example below are rare in an IC package design. Here, a large cline enters a rectangular pad from the wide side. While the trace ends at the center of the pad, the end cap of the trace extends out past the other edge of the pin. This results in a DRC to the nearby via pad.
This is a scenario far more common in an IC design than in a package design because, in almost all cases, the package design does have cline end caps in the same style that a PCB substrate would. However, if the substrate you’re working on will be manufactured to IC process rules, then the end caps don’t truly exist.
Two potential solutions exist here:
End the trace at the right edge of the pad, rather than extending to the center of the pin, or
Remove the end cap
Both meet the requirements. However, the second is more in line with the manufacturing design intent of the IC manufacturing process. You can achieve this in your manufacturing outputs today through the stream out interface. Change your end cap style from the default (Round) to Flush. This will make your manufacturing output more correct but will not change the view above or the DRCs which result.
Cadence is working hard on ways to identify the manufacturing process on a per-layer basis. This will allow you to flag a layer for IC process rules with all the characteristic and behavioral changes thereunto. Instead of the above, the result would be below. No end cap, no extension beyond the pad edge, and no DRC.
There are more differences than just trace end caps, however. Because of this, we are working with our end users and customers, to assess what is required to meet all your present and future needs. If you are an Allegro Package Designer Plus with SI Layout option user, share your requirements and ideas with us as we move forward in these exciting new directions!