IC Packaging and SiP Blogs

There are many reasons a die’s size in the package doesn’t match the design size recorded in the IC layout tool.

For starters, the IC layout doesn’t always include the scribe lines and other manufacturing offsets/adjustments that don’t form a part of the active circuitry of the die but instead exist outside of it. Then, there is the expansion caused by the heating process when mounting the chip to the package substrate. As new nodes become available (or reasonably priced), the die may go through an optical shrink process to reduce its size/cost while improving performance attributes.

All of this means that the die size and pin placement information you, the package designer, receives may need to be adjusted to be accurate for the layout you’re working on. The Cadence Allegro Package Designer tools make no assumptions about the data being imported. If you get information straight from the IC design team (especially if you are working jointly to optimize the bump pattern for both design levels!), it is important that you apply the correct characteristics to the die. This will ensure that the package you design works perfectly – and that it is perfect the very first time!

Optical Die Shrink

Optical shrink is the name for the process by which the chip design contents (all the geometries for the die’s layout) are shrunk down to a smaller node or scaled down slightly to reduce footprint size in the package.

With an optical shrink, the actual die’s size is physically changing. So, too, are the bump positions. It is entirely reasonable to assume that the bump dimensions themselves may be altered in tandem. This means that the shrink affects nearly ALL aspects of the die symbol object in Allegro Package Designer. It doesn’t impact the logical component; no nets are added, removed, or reassigned through an optical shrink. It DOES typically require the pad geometries to be shrunk appropriately.

The package layout tool accounts for this either up-front when the die is imported using interfaces like add codesign die and die text in, when you can indicate the shrink value directly on the forms, or after the fact inside the layout using the die properties command.

If you asked me, I would say the most important consideration is to not make shrink adjustments to the same die incrementally. Don’t start with an unshrunk die and shrink it by 10%, then an additional 5%, and a final 5%. Perform a single 20% optical shrink from the geometry data from the IC designer. This will minimize rounding errors during the shrink (Remember: you’re on a database with fixed accuracy. Decimal values beyond this limit are lost!).

Optical shrink and script values may be applied during die text component import

Before applying any optical shrink, it’s also *critical* that you ensure this hasn’t been applied by the IC designer already. You never want to apply the shrink two times. Nothing will line up in the finished part!

Scribe Line/Lane Widths

For most people, many dies are manufactured on a single wafer in the IC fabrication process. After the wafer is complete, the individual dies are cut out of the wafer. Naturally, this cutting operation removes some material. That is why an area is reserved between the individual die designs. The saw will cut along these lanes.

The scribe line is never exactly sized to the width of the saw, however. A safety margin is left on both sides in case of any slight alignment problem or concern for impacts of the sawing action on the delicate internal routing paths for the die.

Because the entire scribe isn’t removed, then, means that the die is a tiny bit larger than the IC layout’s design extents. That might be the outer limits for where active design elements may be placed/routed, but it isn’t the complete physical part extents.

Optical shrink and scribe may also be applied post-import in the layout

The scribe width, like an optical shrink, can be applied either during symbol import or afterward through the die properties. UNLIKE optical shrink, though, changing these values repeatedly isn’t likely to introduce round-off errors or data loss. We’re only talking a single value per side of the die.

To better understand what happens when both scribe and shrink attributes are applied to the same die, consider this. The optical shrink process reduces the size of every die layout, directly resulting in more of the chips fitting within the size of a single wafer. Unless a different saw is used for the scribing, however, that channel’s width doesn’t need to adapt.

To accomplish this, the optical shrink is universally applied to the die symbol first with the scribe information being added post-shrink to ensure the measurements are accurate for the symbol object.

Thermal Expansion 

We’re not done yet! Thermal expansion is the final adjustment for today (who knows what exciting developments tomorrow has in store for us!). Here, we are worried about the difference in materials and how they react during the application of heat when the die is assembled onto the substrate.

If you’re a regular reader, you’ll know that we covered this specific topic back in May of 2019. Because of that, I won’t go into the nitty-gritty details of the impact thermal expansion differences have on your design.

Being material dependent, thermal expansion is always defined in the context of the individual layout

What I will do, however, is remind you that this is an impact consideration. If you’re working with the same material in both substrates – perhaps mounting the chip onto a silicon interposer – then this step in the system assembly is simpler. It will most likely catch up to you when the interposer is layer mounted to the host package substrate or printed circuit board. Don’t assume that you have escaped the problem. It is just waiting for you a few off-ramps down the highway of system design and assembly.

What Happens with Co-Design Dies? 

Great question! It’s an important consideration. When you’re working jointly with the IC design team and sharing information to allow for co-optimization of the bump pattern on the chip, making sure that all the factors above are included will lead to the most accurate solution possible.

Because the IC designer is probably looking at a view of the pins that is prior to any of the above manufacturing and assembly adjustments and your window onto the same bump pattern sees all of them, a change you want to make may have unexpected complications for the IC designer.

Working in Allegro Package Designer and leveraging a co-design die abstract XDA for the die definition, not only will you be able to see your view, you’ll be validating whether the relocation of a pin will require a shift of other pins (if the pin you want to move is part of a larger macro cell) or will have other negative impacts to the IC layout.

Add to this the top-layer redistribution routing from the IC design and you’ll even be able to compare the relative routing implications in both substrates to rapidly assess whether a change helps the package routing solution more than it harms the IC routing.  

The Results Are In… 

Below, you can see the progression of impact from each of the steps we’ve covered. I have used more significant values in some cases, but only so that you can see the differences better when all four are side-by-side. Optical shrink affects symbol size, pad size, AND pad placement, while scribe lanes only impact the physical symbol’s size, and thermal expansion impacts the placement of connect pads for the bumps at the package level itself.

Making sure your package design is 100% accurate – or as close to perfect as any of us can ever get – is our goal. Apply all the parameters above that impact your layout, avoid surprises as manufacturing deadlines loom, and get an uncompromisingly accurate substrate to market with the Cadence Allegro platform.