Get email delivery of the Cadence blog featured here
As we all know, there are many file formats in which an IC package designer will receive a die from the IC designer. Ideally, it will be in a format such as die text or a co-design die abstract, as these files contain both logical and physical information in a single, comprehensive file. Reality is often not that easy, though; in many situations, you may receive a GDSII or DXF file containing the die outline, pins, and (if you're lucky) signal names. In these cases, the die component needs to be reconstructed from this geometry data.
With 16.6, the Add -> Standard Die -> Compose from Geometry... command makes this previously tedious process nearly effortless. To learn more about just how easy it is to create a die from GDSII source data, read on!
Data imported from GDSII (or Artwork, DXF, and other manufacturing-oriented formats) comes in as simple geometric objects with minimal, if any, additional information. To turn these into an intelligent die component in APD or SiP Layout, run the "Compose Die from Geometry" command. But, before you do, it is important to understand what each layer of imported data represents in the reconstructed die.
As shown in the image below, the compose die tool offers you the ability to identify where the die outline and pin shapes are located. If the information is available, you can even tell it where to find pin names and pin uses (these must be text labels with their origins inside the pin's outline) and the device's name.
The "Find Pins" button will help you verify that you not only have the right layer selected for the pin shapes, but also that the proper pin locations and sizes are represented. In the event that your data doesn't include pin uses, you can set them here if you know them. Later on, you can always configure them using the symbol editing app mode. Don't feel pressured to do it now if you aren't sure.
The final thing you need to tell the system is whether the data as loaded represents the definition view of the die, as it would be shown in an IC layout tool, or, if it is in the orientation, the die will be mounted in the package (for instance, if you are reconstructing an entire package substrate using data output from a different package layout tool). Once your choices are complete, the die will be generated and you can place it into the current design
When placing the constructed die, you have even more options to get things just the way you want them for the current substrate. Pick the appropriate attachment method, layer for the pins, and even add scribe and die shrink (if the data is coming directly from your IC designer).
Is this a flip-chip device and you want to use a pre-defined library padstack to represent the landing pads on the package substrate? Not a problem! The tool gives you everything you need for that. In fact, you can even have it automatically define the physical pin numbers - information not used by the IC designer at all, typically - on your behalf given a simple indication of the pattern you want applied. Whether it is, an alphanumeric grid or a spiral pattern of numbers only, the tool will add this for you at the mere press of a button.
Once you're finished, you can assign nets to your newly instantiated die component or place it into a die stack or an open cavity. Or, get straight into the design work and begin wire bonding and creating escape routing. The choice, as they say, is entirely up to you.
So, don't delay! Update to 16.6 today and streamline your communications with your IC design partners or quickly reconstruct a package design begun in another design tool with the compose die from geometry command.
Have a comment? We'd love to hear from you!