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Design variants are a common phenomenon, whether you design package substrates or PCBs. You may source a resistor from multiple vendors, and part of the design flow includes generating a bill of materials (BoM) which lists all the parts that go on a version of the board. Useful information, certainly when it comes to figuring out how much each substrate costs you to make.
But, swapping one 100ohm resistor for another is far from the only reason you might need to have variants of your layout database – particularly when it comes to package substrates.
I’m sure you’ve bought a video card or other component which gave you the option to choose between 4GB, 8GB, or 16GB of on-board memory. One way to achieve this is to have different stacks of memory die components but with the same ball pattern for the BGA. Sounds like a variant situation to me!
Then, there’s the idea of wanting to verify your design at best and worst-case scenarios for manufacturing tolerances. If your clines end up 1 UM wider than designed, what impact does that have on your SI results? Where are the likely points of failure if your shape is undersized by a given amount in the final package?
These situations (and many more) are ones that the SiP Layout tool’s variant tool makes seamless for you to manage. Design once and manufacture multiple times. To learn more about two of the most common uses for the tool, keep reading.
The master design contains all variant options in one easy to edit layout database. For the rest of our talk today, I’ll be using a three-die design which has two options – one with one die and the other with two. In the master design, this looks like the following image in the die stack editor:
A memory stack is doubtless the most common component-based variant we see with the tool today. If you want to design your bond shell with finger locations that will work for all versions of die, it is most effective to connect all the dies up to the fingers and push and shove the pattern around with knowledge of everything.
Not only does this ensure that you don’t miss any connections (or connect the wrong nets up to something), it eliminates the innate possibility of using multiple SiP databases and moving a finger in one but neglecting to make the same change in one of the other versions. Why give yourself the opportunity to make a mistake you don’t have to?
The image above is one I’ve captured from a simple package design I created. The complete design has 3 die components and a BGA. Here, I’m working to define a two-die variant. From the list of available components, I’ve removed DIE1, which in my case is the bottom die on the first DIESTACK layer above top.
In addition to this, I can remove that layer from the stackup for the exported variant database. This leaves everything clean and minimal. But, more importantly, when the variant goes out and the DIE1 component gets stripped out, the bond wire connections to the die are also removed. If I had mistakenly had a bond from DIE2 down to a pin on DIE1, I will know this immediately in the variant database because I’ll see the ratsnest showing the missing connection. Handy!
Other things that get updated in the exported design? The die stacks are compressed to show you the true height of each component. The bond wire lengths are recomputed to give accurate lengths for you to judge the total length of wire required to manufacture one part. And, the 3D tool will show you the bond wire paths for 3D DRC spacing checks and bonding simulations you may need to run. If you were to bring the variant design to Sigrity, it would have a fully accurate model for simulation with no additional work needed from you as the designer. Our two-stack variant’s stacked die arrangement and the corresponding 3D view are shown below. A much more realistic model now that Die 2 doesn’t block the pads of Die 1 from being bonded.
They say nobody is perfect, right? I’m not, at least. And your manufacturer probably gives you some details on the accuracy level to which they can create shapes, pads, traces, and other geometries from your design in the final component.
If they tell you that line widths are +/- 1 UM, shapes may be over or under by 2 UM, and your pads may be 3 UM off your expressed value; that can have a definite impact on the electrical performance of the design. While your spacing constraints will make sure that these tolerances don’t cause shorts in your design, how do you easily assess the range of variations’ impact on the signal integrity characteristics? You guessed it! The variant tool!
The second section of the form, shown below, allows you to enter the minimum and maximum discrepancies for the different types of geometries. Here, I’ve set the chart for all the layers to be the over and under ranges I just talked about in my fictional example. Note that I hid the unnamed dielectrics using the option at the bottom to make my chart easier to read. I’ve also removed the WB_3 and WB_2 layers, as this is the one-die variant of my original design.
What happens when I generate this variant? If I generate the min database, then all my clines will have their widths reduced by 1 UM, the shapes by 2 UM, and the pads will be reduced by 3 UM.
By the way, don’t think that you must use absolute values here. If you enter a percentage, that’s equally valid – meaning a 1% difference on a 100 UM trace will reduce it to 99 UM, while a 10 UM trace will only go down to 9.9 UM. You can mix and match in the chart, too, depending on the manufacturing methods for the different layers. Please see your foundry partner for complete details!
If you were interested in how this looks different than the two-die variant, check out the same views, below, for the one-die design:
Drill hole diameters can be biased as well. I didn’t set them in this example to highlight that; of course, you can choose to leave any of the options blank that you want.
You’ve got your variants configured. You’ve routed your design. What happens when you press the button to export your variants, shown below?
Once you pick your options (we recommend adding the FIXED property to the components, so that you don’t make changes in a variant that might conflict with the master design), you may export the active variant only or all the defined variant configurations. Each will be created as an individual SiP database file on disk. The file will be tagged as a variant, so you always know that it came from a master, and what that master design is.
Each design is now a complete, ready-to-go package design. You may immediately run it through the 3D Canvas or Sigrity tools, generate artwork data from it, do additional verification through a downstream tool of your choice such as PVS, or pass it to your manufacturing partner for verification.
Now that you’ve seen the two most typical scenarios that the variant interface enables, perhaps you’ve got other ideas to explore. Whether you are looking to try defining multiple package variants for the same die(stack) or explore different core layer configurations and materials, you’ll find a high degree of configuration. Define as many variants as you want within the same database.
One parting word of advice, however. It pays to define the master design’s cross-section with all the necessary layers before starting to set up your variants, just as we strongly urge you to add all your components first. If you don’t, then when you add these to the design later, you’ll have to cycle through and add them to all the appropriate variants. That can be easy to forget, so why risk it?
Should you find a flow that isn’t enabled by the tool today, please share it with us. Whether it’s a comment here in the blog or a conversation with customer support or your sales rep, we want to hear about your needs!