System Design and Verification Blogs

There’s nothing like the heat of a DAC demo to stress new technology and the engineers behind it! Such was the case at DAC 2018 at the new locale of Moscone Center West, San Francisco. Cadence and AMIQ were two of several vendors who announced and demonstrated support for the new PSS v1.0 portable stimulus standard. An SoC example was used to show the PSS v1.0 interoperability of Cadence Perspec System Verifier and AMIQ Design and Verification Tools (DVT) Eclipse integrated development environment (IDE). Read more about the history of PSS here.

Figure 1: AMIQ’s DVT Eclipse IDE with Accellera PSS v1.0

With the new PSS support in DVT Eclipse IDE, verification engineers can develop robust portable stimulus descriptions in much less time. Features now available for PSS include on-the-fly compilation and error detection with quick-fix proposals, hyperlinks to jump to declarations and usages, context sensitive auto-completion of PSS constructs, structural views for browsing type and component hierarchies, project database queries, diagrams, rename refactoring, and source code formatting. Engineers specifying PSS models now have the same benefits as the users of the other languages and formats that DVT Eclipse IDE supports, including SystemVerilog, VHDL, e, C/C++, SLN, UPF, and CPF.

This was no ordinary DAC demo, not in the slightest. Cadence and AMIQ decided to let customers use their tools with the brand new language. Choosing a simple open source SoC example, and some pre-designed PSS v1.0 code (both DSL and C++ syntaxes), users were able to quickly learn about the platform, PSS, and the tools. Users were given a task to modify the PSS to do something different. Read more about the portable stimulus coding contest here.

Figure 2: The Cadence Portable Stimulus Coding Contest

Pre-registered and walk-up contestants included large and small semiconductor companies, EDA companies from the Accellera Portable Stimulus Working Group (PSWG), and even some Perspec-certified service providers from the Cadence Verification Alliance program:

• Agnisys
• Alpha Scale
• ASD Actel
• Broadcom
• Cavium
• CVC
• Doulos
• Microchip
• Microsemi
• Microsoft
• Multiware
• Qualcomm
• Tecasystecnologs
• Vayavya
• Western Digital
• Willamette HDL

Figure 3: Reps from Western Digital and Qualcomm compete head-to-head coding PSS v1.0

The Perspec PSS coding contest was a real hoot. I enjoyed this DAC experience more than any DAC for over 15 years. I will announce the winners of the contest in a subsequent blog. For now, read more about Perspec and PSS v1.0 here. Read more about AMIQ’s DVT Eclipse IDE here.