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If you’re not familiar with the series of DVClub events held in North American, Europe, and Asia, please consult my most recent blog post for a brief history. These events offer a unique opportunity for hands-on verification engineers to network with their peers, hear from one of their own about an interesting recent project or a new verification technology, and chat informally with the sponsoring vendors about their solutions. Cadence has supported DVClub since its earliest days and remains an enthusiastic sponsor.
Today I’d like to focus on a particular talk that I mentioned briefly last time. At the October 12 meeting of DVClub Silicon Valley, Dave Brownell from Analog Devices presented “Portable Stimulus: The Next Step in Verification Productivity” to a warm reception. Dave is a well-known verification expert and an active participant in the Accellera Portable Stimulus Working group (PSWG). Since Dave will reprise his presentation at DVClub Boston next week (November 9 in Westford), it seems timely to review and comment on some of his main points.
Dave opened with a summary on the state of verification productivity, which is not scaling as the complexity of design projects continues to increase. He summarized the history of design verification into six phases:
Dave next addressed why there is a need to move to the sixth phase by pointing out the UVM does not scale from block to system level or from simulation to hardware verification platforms. It also separates hardware and software verification, which are intertwined ever more closely as many large designs adopt system-on-chip (SoC) architecture. He showed the typical verification process, with little reuse or shared knowledge between the steps.
What are the challenges to verification reuse and better productivity? Dave summarized these in a diagram that captured many of the most important aspects that the PSWG’s upcoming standard is intended to address. There must be a portable way to describe verification intent, including the register and memory map, enabling generation of tests that run on the SoC’s embedded processors while synchronizing with the chip I/O ports when needed. This model must capture system knowledge and the generation must be platform-aware with support for debug of complex tests.
The third step in Dave’s argument for a new verification solution focuses on three goals. The first is reuse of the generated tests, which includes bidirectional portability from IP to SoC and from simulation to silicon. The flow must be reversible so that a bug found in silicon has a reasonable chance of being replicated in block-level simulation for debug purposes. The portable stimulus model must be at a high enough level of abstraction to reduce the time to “author” tests and to serve as an efficient means of sharing intent across all the project stakeholders.
I liked the “Re-Imagined Development Process” slide because it was the final step in Dave’s argument for evolution in verification. It succinctly showed how the portable stimulus standard (PSS) will serve the needs of project teams from architecture through production test and how the generated tests will run on every verification and test platforms. He also introduced the term “use case” which highlights that the generated tests represent realistic user scenarios and true system-level behavior.
I’ve hit some of the highlights of Dave Brownell’s DVClub talk, but trying to cover it all in detail would take a whole series of blog posts. I encourage you to attend his talk in Westford next week if you can or to contact him if you want to find out more. As a DVClub sponsor, PSWG officer, and deeply interested party I’d like to thank Dave for his help in promoting discussion on this very important verification topic. Finally, I’d like to echo his invitation to join the PWSG to help us produce the best possible standard. We hope to hear your voice at a future meeting,
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