System Design and Verification Blogs

Vegas, here we come. All of us fun EDA engineers at once. Be prepared, next week’s Design Automation Conference will be busy! The trends I had outlined after last DAC in 2018—system design, cloud, and machine learning—have only grown stronger and are causing significant changes in the development landscape. At the bottom of this post you can find my suggested DAC schedule for you if you are interested in verification. Key partners and customers like AFRL, Arm, Green Hills Software, AMD, Altair, Samsung, Tortuga Logic, Microchip and Intel will be presenting at our Cadence DAC Theatre this year again, you do not want to miss them!

But first things first - in my last Blog on SemiEngineering’s “Frankly Speaking” called The Changing Landscape Of Hardware-Based Verification And Software Development, I had asked what’s next in this space and suggested that DAC will likely show more innovation in the hardware-assisted development space. In AI and Machine Learning Drive New SoC Verification Choices, I had outlined the traditional speed degradation of prototyping performance as designs grow bigger, specifically beyond 400 million gates, and had suggested that it’s about time that somebody addresses this issue.

Well, we just did. And you can see it at DAC! Earlier this week we introduced the Protium X1 Enterprise Prototyping Platform, which marks another significant step for prototyping.

Back in 2017 we introduced with Protium S1 what was probably the biggest innovation in prototyping by reducing the bring-up time, the time from RTL to working prototype, by an average of 80% compared to classic prototyping, which was mostly manual. At the time we did this with an automated flow for the partitioning, clocking, and memory modeling together with an integrated layout flow for the Xilinx FPGAs.

This week we extended prototyping into the datacenter with a scalable, rack-based Enterprise Prototyping System – Protium X1. You can find more information on our landing page and in the Breakfast Bytes’ Blog Protium X1: FPGA Prototyping for the Enterprise. The main design target was to reach up to 5 MHz speed for billion gate designs, out of the box, with a unified flow from Palladium Z1 emulation. The main targets are the really large AI, ML, 5G, Graphics and server designs for which Desktop Prototyping drastically decreases in speed due to cabling. We also targeted single FPGA granularity that allows up to 48 users per rack and is intended for small designs like in storage, IoT etc.

To give you a visual of what just happened, up to now the upper right spot for prototyping in the graph below was really empty. If one wanted to go to high capacity (think 1 to 2 billion gates) and high performance (think 5 MHz and more), there was really no prototyping system to allow you to do that without a lot of manual work (even though some claimed capacities of up to 1.6 billion gates). Protium X1 changes that. It re-segments the market into Desktop Prototyping and Enterprise Prototyping. In our new hardware portfolio, as shown below, Palladium Z1 Emulation will always, because of its custom processor, be best for predictable, fastest compile (think no FPGA layout) and most advanced, flexible debug, as well as use model versatility - the key properties for successful hardware verification. Protium S1 and Protium S1-G (our single FPGA system) serve the Desktop Prototyping market for software development and hardware regressions. While Protium S1 extends to beyond 400 million gates,  like other Desktop Prototyping systems it slows down because of cabling and general signal length. Protium X1 enables high capacity high speed prototyping - billion gates at multiple Mhz - while also providing single FPGA granularity for multi-user access, and of course we maintained congruency with emulation using our unified compile flow with Palladium Z1.

Please check out our Protium X1 press release and the parallel press release about NVIDA’s usage for GPUs.

But wait, there's more!

Security and safety are important themes for quite some time now, we earlier this year announced our strategic partnership with Green Hills.

Earlier this week Tortuga Logic announced how they collaborated with Cadence and used Palladium Z1 emulation in the Cloud to run their Radix-M platform capable of performing security validation of firmware on complex SoCs. Radix-M identifies and prevents unknown firmware vulnerabilities. It also automates previously manual processes firmware engineers and SoC security teams conduct using the existing hardware- and cloud-based Cadence® Palladium® Z1 Enterprise Emulation Platform for seamless hardware and software execution

So what to see at DAC regarding verification?

Here is your suggested DAC schedule for this year:

Monday, June 3^rd

• 10:00am: Cadence, “Smart JasperGold Formal Verification Platform”, Cadence Theatre
• 10:00am: “Verification Throughput and Performance”, Cadence booth
• 12:00pm: “Verification Throughput and Multi-Level Abstraction”, Cadence booth
• 12:00pm: AFRL, “AFRL Palladium and Cloud Execution Environment”, Cadence Theatre
• 12:30pm: Arm, “Hardware/Software Debug for Arm-Based 5G”, Cadence Theatre
• 2:00pm: “Verification Throughput and Smart Bug Hunting”, Cadence booth
• 4:00pm: Green Hills Software, “Towards Secure and Safe Software Development Using Green Hills Software and Cadence Technology”, Cadence Theatre
• 5:00pm: Arm, Cadence, “Optimizing Hardware/Software Development for ARM based Embedded Designs”, Designer Track Poster Session
• 5:00pm: Cadence, “Accurately Modeling ASIC Memories in FPGA-based Prototype Systems”, Designer Track Poster Session
• 5:00pm: AMD, “SoC Power Management Test Scenarios with Portable Stimulus”, Cadence Theatre
• 5:30pm: Altair, “Streamlining Palladium Workload Management with Altair Hero”

Tuesday, June 4^th

• 10:00am: “Verification Throughput and Performance”, Cadence booth
• 1:30pm: "Intel, Low-Power Validation of Heterogeneous SoCs Using Portable Stimulus Standard", Cadence booth
• 2:00pm: “Verification Throughput and Multi-Level Abstraction”, Cadence booth
• 4:00pm: “Verification Throughput and Smart Bug Hunting”, Cadence booth
• 4:30pm, Samsung, “Accurate Power Analysis Leveraging Emulations”, Cadence Theatre

Wednesday, June 5^th

• 11:30am – 1:00pm, “Optimizing Verification Throughput for Advanced Designs in a Connected World”, Westgate Conference Center – Paradise South Room
  • Moderated by Brian Bailey, Semiconductor Engineering
  • Tran Nguyen, Arm
  • Raju Kothandaraman, Intel
  • Dale Chang, Samsung
  • Paul Cunningham, Cadence
• 12:30pm: Tortuga Logic, “Enabling System Security Validation with Radix-M on Palladium Platforms”, Cadence Theatre
• 1:00pm: Microchip (with Oski), “Metrics-Driven Formal Sign-Off of PCIe PCS”, Cadence Theatre
• 2:00pm: Cadence, “Early Software Development for Billion-Gate SoCs with Protium X1”, Cadence Theatre

There are a lot of other Cadence activities, including our Expert Bar, you can find the latest schedule of Cadence events here, and the full Cadence Theatre schedule is here. Also, join us for the "Second Annual Pi Contest" in the ChipEstimate.com Booth at DAC for a chance to win a Raspberry Pi 3 Model B. Sign up to learn more about Portable Stimulus and see your results immediately using Cadence's Perspec System Verifier on the cloud. The person with the fastest daily score wins the prize!

See you in Vegas!