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For a number of years now, AMD has been applying an advanced acceleration use case referred to as hybrid verification. It’s basically a verification run utilizing the strengths of two verification engines -- in this case, a virtual platform and an emulation platform. This hybrid verification use case helps AMD achieve application-level performance well beyond traditional emulation speeds, resulting in improved debug with virtual platform debuggers. AMD extended their hybrid emulation use case to run real application workloads while measuring power events in the design in order to increase the confidence in architectural power management features ahead of silicon availability. AMD's paper, presented at CDNLive Boston 2014 in Massachusetts,discusses some of the challenges that were overcome and the results that were achieved using hardware-assisted verification with the Palladium XP platform. The paper breaks down the power event monitoring into three stages – stimulus creation, data collection, and analysis, as shown in Figure 1.
Figure 1: Power event monitoring stages
At the end of the day, AMD's paper aims to show the user community how to measure power events with hardware-assisted verification and how to overcome some of the challenges of measuring power events.
Technology Spotlight – In-Circuit Acceleration
Several underlying technologies are required to enable the hybrid verification environment with a virtual platform and hardware-assisted verification acceleration. One such critical technology that enables hybrid verification is In-Circuit Acceleration (ICA). ICA is a Palladium XP platform-specific technology that combines different design models or abstractions into a single unified run, enabling a flexible system-level validation environment. Not only applied in hybrid verification use case, such as the one that AMD applied, it has a broader use case enabling the user community to leverage both the high-speed real-world interfaces of traditional in-circuit emulation environments combined with the advanced analysis capabilities available in RTL simulation, into a single heterogeneous platform for system-level verification. In broad terms, ICA combines two traditional modes of in-circuit emulation and acceleration into a single combined run. To learn more about how this technology can be applied in your verification environment, give your applications team a call and we’ll go into more details.
Author notes: This article is part of a series of "double-take" articles aimed at highlighting an actual user application of a Palladium XP use model along with a technology highlight leveraged in the application.