Google FeedBurner is phasing out its RSS-to-email subscription service. While we are currently working on the implementation of a new system, you may experience an interruption in your email subscription service.
Please stay tuned for further communications.
Get email delivery of the Cadence blog featured here
It’s now official: Perspec System Verifier is rated the #1 product in the #1 category of Portable Stimulus, according to the 2017 EDA User Survey published on Deepchip.com. There were 33 user responses in favor of Perspec as the #1 tool, and driving Portable Stimulus into the #1 EDA tool category. They wrote 3,097 words describing their thoughts and opinions on what they liked about Perspec.
“What most users liked about Perspec was the payoff they got with it after the initial ramp-up. Big ‘likes’ for its ARM libs, its coverage-driven pattern generation, and of course stimulus reuse across derivative SoCs and through all the stages of SoC development.”, John Cooley, Deepchip.com
The survey sought input from users with the following question:
Q: "What were the 3 or 4 most INTERESTING specific EDA tools
you've seen this year? WHY did they interest you?"
Selected User Comments
There are many awesome user comments in the survey, some of the best are shown here:
“We have been using Cadence Perspec for a while now. We use it to reuse stimulus across all our derived chips from a base chip, and reuse our stimulus across platforms. We currently use it with Incisive and Protium.”
“With Perspec our early IP guys can talk to our SoC guys, who can talk to our functional verif. guys, who can talk to our post-silicon verif. guys. Its automated test generation based on the formal declaration of *action* is great for complex system level tests -- which would not be possible to create manually.”
“Perspec's coverage-driven pattern generation allowed us to create scenarios that we would not have created manually, due to their complexity.”
“The Perspec GUI is useful when you write and review scenarios. We also like how it works well with Indago when it comes to debugging long and complex patterns.”
“Easy to model complex SoCs using Perspec's SLN language. (Cadence donated SLN to Accellera as the starting point for PSS, and the majority of PSS is now based on SLN concepts, though Accellera changed some of the notations.)”
“Perspec's SLN model, which we used to create our scenarios, is a good solution for us. It brings some abstraction from our C patterns, and makes maintenance and reusability of our patterns easy.”
Read the rest of the user comments in the Deepchip.com survey report.
Strengths of Perspec System Verifier
The most commonly mentioned reasons users prefer and voted for Perspec include:
Cadence Innovations are the Basis of the Accellera Portable Stimulus Specification (PSS)
There is one topic that users are still coming to understand, and the current confusion can be found in some of the user comments.
When Cadence developed Perspec we defined a system level notation (SLN) language that is used to model the SoC and SW under test and the scenarios that define the generation of portable tests. This language was enhanced while working with some of the most demanding users in the industry over the course of several years of industrial application.
When Accellera formed the Portable Stimulus Working Group (PSWG), Cadence chose to donate SLN, and most of the resulting PSS v1.0 draft specification is based on SLN concepts. Even after the changes introduced via the standardization process, even a casual observer can see the roots of SLN in PSS examples when held next to each other. The expression of PSS in either its DSL or C++ syntax can also be traced to the SLN contribution baseline.
We plan for Perspec to support both syntaxes of PSS shortly after the standard is officially ratified, and will continue to support SLN. Users will be able to use any of the syntaxes and mix them as desired, to provide maximum reuse.
For more information, including how PSS can address your specific needs (low-power, coherency, memory virtualization, multi-IP scenarios, or interconnect testing), contact firstname.lastname@example.org.