Renesas Leverages Palladium + System VIP Solution for System Verification and Performance Optimization

10 May 2022 • 5 minute read

With the shrinking development time and growing designs, verification teams often find it challenging to verify bus performance. Faster execution time, test bench creation with less effort, and efficient test pattern generation are often required. Renesas also faced a similar challenge: verifying bus performance in their chips by analyzing bandwidth and latency over time. They decided to use Cadence tools to mitigate such issues and used a series of operational flows with AVIP and ATP integrating Cadence tools. Here, Palladium was used to mitigate issues due to stretched emulation time, Perspec’s portable stimulus was used for automatic test pattern creation, and Cadence System Testbench generator assisted with efficient testbench generation.

The collaboration with Cadence resulted in a comprehensive emulation package and a new efficient bus performance verification scheme design that helped Renesas to achieve faster turnaround time, efficient test bench creation as well as test pattern generation.

Renesas witnessed a stellar performance with 160x speedup in actual simulation or emulation itself along with 16x speed up in bandwidth and latency calculation and extracting the maximum and minimum bus performance with the System Performance Analyzer.

Bus Performance Verification Challenges

Renesas faced three major challenges during bus performance verification:

Long execution time – RTL simulator-based execution takes more time leading to a bottleneck in the development turnaround time.
Many efforts to create a test bench – It takes a few weeks to build a test bench, as active and passive VIPs need proper allocation with their bus interface configuration.
Tough test-pattern creation – Executable test patterns, in which several transactions issued by bus masters with multiple threads compete, are necessary to verify.

Solution

To mitigate such challenges and accelerate the execution times and achieve effortless test bench/test pattern creation, Renesas decided to deploy and integrate three tools (mentioned below) from Cadence with scalability that allows reusability in case of any design change:

In collaboration with Cadence, Renesas developed a variety of features to improve their hardware emulation scalability. It used the new integration approach with scalability by utilizing hardware emulation on Palladium with AVIP and C++, automated testbench creation and performance analysis, and System Testbench Generator ATP test-pattern generation with Perspec’s Portable Stimulus.

Cadence System Performance Analyzer, Perspec, and Palladium work together to tackle these challenges by providing vast upgrades in speed and precision across the development process.

Why AVIP Instead of VIP?

AVIP is synthesizable to a hardware map and operates at HW speed.
AVIP has a C++ native interface, which is 10x faster than the SystemVerilog interface. Also, it allows speedy communication between the hardware and software
The AVIP also has AMBA/ATP (Adaptive Traffic Profiles) implemented in the master AVIP, which is useful for acquiring scalability as well
Renesas and Cadence created support for concurrent traffic profiles and more—and it’s compatible with Palladium and Perspec

Acceleration of Execution

To take the advantage of HW emulation (Palladium) with scalability, Renesas, in collaboration with Cadence, developed the below techniques in addition to AVIP and C++ interface on AVIP:

ATP implementation in master AVIP
Concurrent traffic Profiles

The HW part of ATP was implemented in AVIP for getting the high-speed benefit. It is controlled with C++ Interface for simulation acceleration as there is no need for compilation every time.

Less Effort for Testbench Creation and Performance Analysis (System Testbench Generator)

The System Testbench Generator was used to describe their testbench topology through IPXact or CSV and automatically generate a ready-to-use UVM SystemVerilog testbench for simulation or C testbench for emulation.

For exhaustive functional verification, it generates fully functioning UVM SystemVerilog environments that come complete with Verification IP, scoreboard, clock and reset generation logic, test sequences, routing model with system memory map, and more.
For subsystem and system integration verification, it generates C-based verification environments that can run in simulation or in Cadence Palladium and Protium hardware platforms.

Main Capabilities

Generation of fully functioning UVM SystemVerilog verification environments from user-supplied meta-data for simulation flow
Generation of C-based verification environments from user-supplied meta-data for simulation, acceleration, and emulation flows
Support of functional verification and performance analysis
Fully compatible with Cadence Perspec System Verifier for creation of portable stimulus
Per-user configuration, generated environments include Simulation
Verification IP (VIP), Acceleration Verification IP (AVIP), system-level scoreboard, routing model with system memory map information, pre-generated ready-to-use tests, and more

Efficient Test-Pattern Creation and Stimulus Portability (Perspec)

Creating a test pattern is critical – it needs time as well as skills to cover all corner cases. Renesas in collaboration with Cadence used the below techniques using Perspec to efficiently create complex case scenarios:

Automated Synchronization using enhanced IPC
Test-pattern with DPI-C generation – For every master at the same time
Perspec model for AXI – Models suitable for AXI as well as concurrent traffic profiles are developed by Perspec
Stimulus Portability – User-defined profile can be modeled

The integration of the System Performance Analyzer, Perspec, and Palladium is shown in the schematic diagram.

Outcome

The test, performed on an SoC with about 170 bus masters, had significant improvements in acceleration and efficiency. In the assembling stage, Renesas saw a 5x efficiency boost using System Testbench Generator and Cadence AVIP. When executing the simulation or emulation, a 12x efficiency boost in the creation of test patterns, along with a 160x speedup in the actual simulation or emulation itself was witnessed. Even the post-run analysis was faster, with a 16x speedup in calculating bandwidth and latency, time analysis between master and slave buses, and extracting the maximum and minimum bus performance with the System Performance Analyzer.

Summary

Accelerated execution, effortless testbench creation, and more efficient test-pattern creations were the major requirements for bus verification. Renesas, in collaboration with the Cadence support team, developed a new integrated approach with scalability utilizing hardware emulation on Palladium with AVIP and C++ I/F, System Performance Analyzer, Scalable ATP test-pattern generation, and stimulus portability on Perspec. By applying this practical flow to our SoC design, which has about 170 bus masters, significant improvements in acceleration and efficiency were achieved.