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One of the main benefits of moving the design entry point up in abstraction from RTL to SystemC/TLM is faster verification turnaround. Higher abstraction contains much fewer details, so simulation at that level runs faster and debug is much more productive.
But in order to reduce overall verification turnaround, the work done at this level needs to be leveraged to greatly reduce the amount of work done at subsequent levels. Otherwise it just becomes an extra step. This means that verification at higher levels of abstraction needs to be an extension of your existing metric-driven verification methodology plan so that you can verify functionality at the abstraction level where it is introduced. Then instead of re-verifying at lower abstraction levels, you can just regress it while focusing verification on functionality that is newly introduced when the lower levels of abstraction allow for more detail.
Yoshi Watanabe, a Sr. Architect at Cadence who has been working with key partner customers to extend their existing environments up to SystemC/TLM, recently explained his approach in a webinar which is available for replay. It is titled "Speed Verification Turnaround by Extending MDV to TLM." You can access it here:
If you're looking to speed verification turnaround (and who isn't?), this is a must-see.