System Design and Verification Blogs

Cadence continues to be a leader in SoC verification and has expanded our industry investment in Accellera portable stimulus language standardization. Some customers have expressed reservations that portable stimulus requires the effort of learning another domain specific language. Given that verification engineers are "always" behind schedule on their current and next project, this is an understandable concern. However, the value of portable stimulus far outweighs the cost. I'm reminded of Henry Ford's famous quote: "If we did what customer's asked for, we would be building faster horses."

Realizing the benefits of this new technology can be reduced through examples, methodology, documentation, and training. This week, Hardent and Willamette HDL announced they were creating an Accellera Portable Stimulus Standard (PSS) training course with Cadence based on Perspec System Verifier. Customers get the best known methods in training from Willamette HDL, and the content and application expertise of Cadence built into a training course and exercises.

Willamette HDL is an experienced training company, as demonstrated from their widely subscribed UVM/System Verilog verification, along with Verilog and VHDL courses. Their technical and innovation leadership is the reason Cadence chose to collaborate with them on this first ever PSS course for Perspec. In the training you'll see how to create PSS for SoC level scenarios, and then port (aka reuse) the scenarios at the IP level (coreless). Creating PSS for this kind of scenario portability is the singular goal of the technology.

Reach out to Willamette HDL here. You'l be glad you did!