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Every design engineer knows something about glitch but for many the details are a little fuzzy, especially since the topic has recently evolved well beyond the original, simple analysis. I will use this posting to sketch a quick overview of the state of the art in Tempus glitch analysis as an orientation for the non-expert.

Fundamentally, glitch noise is caused by capacitive crosstalk between wires that allows a signal transition on one wire, the aggressor or attacker net, to induce a voltage spike on a neighboring wire, the victim net (Fig.1).

Figure 1. Glitch noise is a voltage bump on a quiet victim net caused by capacitive coupling to an aggressor net that is switching

The dangers of glitch noise are that the wrong value can be stored in a flip-flop, or that a false transition on a clock/control signal triggers a spurious transition in a sequential element. If the glitch bump is small it is probably harmless, but if it is big enough it can cause harm.

The first question that crops up is how glitch noise is different from timing signal integrity.  They are both caused by exactly the same capacitive crosstalk effect, but the distinction is in the activity of the victim net: For timing signal integrity, the victim net is switching and the crosstalk causes a change in delay. Glitch analysis assumes the victim net is quiet (not switching) and the crosstalk creates a positive or negative voltage bump.

Early Threshold Models

Glitch analysis solutions strive to attain 2 key goals. The first is for accuracy of the predicted glitch as compared to SPICE and the second is to avoid reporting too many insignificant glitches and correctly flag only the glitches that matter. In the beginning, glitch analysis simply tried to identify voltage bumps whose maximum amplitude exceed a certain threshold – usually expressed as a percentage of the supply voltage. This quickly proved overly pessimistic because many tall, narrow glitch spikes are not in fact problems.  Indeed, the danger posed by a glitch is tied to the energy it contains and whether this is sufficient to cause the transistors on the receiver input pin to switch or not. This energy is related to the integral of the area under the graph of voltage over time.  Tall, thin voltage spikes exceed the maximum voltage threshold but are too brief to affect the input pin transistors.

So the industry moved on to a more elaborate model that captures both the width and the height of the glitch. This model is sometimes called the “noise immunity curve” and is typically found in NLDM library models. Unfortunately, this model has also proved to be inaccurate and unreliable, especially for advanced finFET nodes, and is now considered obsolete. 

The RIP and the ROP

To determine a more meaningful and reliable glitch filtering threshold Tempus has moved beyond these ‘Receiver Input Peak’ (RIP) models for glitch and now uses a ‘Receiver Output Peak’ (ROP) model.  The ROP is the response by the first stage in the driven cell to the glitch on the input pin.  CMOS logic stages are low pass filters; the first stage will either attenuate the glitch if it is small or amplify it if it is big enough.  But the key point is that the ROP, the response by this first stage to the incoming glitch, is the correct way to judge whether the glitch is significant or not (Fig.2). So Tempus filters glitches based on the actual effect they have on the receiving gate. This ROP model has proven to be much more accurate and more reliable in filtering out insignificant glitches.

Figure 2. The filtering of glitches in Tempus is determined by calculating the response of the receiver to the glitch.  Glitch thresholds must be determined by maximum ROP peak, not RIP.

Older tools like CeltIC used to calculate the ROP response by invoking SPICE to run simulations under the hood. But today this is no longer necessary with standardized CCS-Noise libraries (also cdB and ECSM-SI libs). These contain Voltage-in/Voltage-out tables for the first and last stages of every cell timing arc which allows faster and more direct calculation of the ROP for quick and accurate glitch filtering.

Glitch Propagation

Glitch propagation through inverters is not uncommon in today’s circuits and especially in clock trees. Glitch propagation is important for 2 reasons: First, one can argue that unless a glitch causes a faulty value to be latched-in it really does no harm. So glitch propagation can be used to determine if a glitch really needs to be fixed.  In practice, most customers require all glitch failures to fixed in the early stages of design. It is only in the final stages of timing closure that fixes for non-latching glitches are waived.

The second reason to consider glitch propagation is that it takes into account how a small, harmless ROP on the output pin of a single stage gate can combine with a small, harmless crosstalk on that same pin to create a significant summed effect that causes a glitch failure. Without considering glitch propagation, each individual effect on its own would be filtered out as insignificant, but together they cause a glitch violation.  A significant contributing factor in this regard is driver weakening.  Even a small ROP will serve to weaken an output driver’s ability to maintain a steady voltage. This means that the output net becomes more susceptible to crosstalk induced voltages and thus larger glitch amplitudes (Fig.3).  This driver weakening effect is also considered by Tempus glitch propagation.

Figure 3. A small ROP on an output pin will weaken the driver and make it more sensitive to additional crosstalk to create a glitch failure

Reporting and Automatic Fixing

Tempus ECO can use its tight integration with Innovus implementation to automatically fix glitch failures through surgical design changes, including upsizing the victim net driver and inserting buffers in the victim net. Tempus is also able to go back through the logic fan-in cone of a glitch failure and report the original source of a propagated glitch. This is important because it is much more efficient to fix the original source of a glitch rather than fix all downstream propagated glitches that are a consequence of this first failure.

Summary

Tempus has a rich and sophisticated set of capabilities to accurately calculate the true impact of glitch noise and to efficiently consider the impact of glitch propagation. This competence is based on many years of experience working with customers on glitch and the codification of advanced glitch models in standardized library formats like CCS-N. Tempus ECO provides an automated path to quickly and easily fix any glitches in the layout through direct integration of Tempus ECO with Innovus implementation.