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A new paradigm shift is now happening in the electronics industry with systems design. The conventional thinking of designing an electronic system with a single monolithic SoC is changing to using a multi-die approach with chiplets and advanced packaging technology. This reversal in thinking is opening a new era for systems design.
So, what are chiplets and chiplet-based systems?
Well, the chiplet idea has been around for several years but is gaining momentum with the maturing of advance interconnect and packaging technology. Chiplets are known good dies typically with a single functionality and include a wrapper with small micro-buffers, level-shifting capabilities, test enabled, and leverage a communication interface like the Advanced Interface Bus (AIB). They can be thought as specialized silicon blocks or IP blocks that are design and fabrication process optimized. This enables them to be designed as small as possible which increases its yield and minimizes its cost.
Figure 1. Chiplet-based system made of multiple chiplets on an interposer.
A high-performance system can then be built by selectively mixing and matching chiplets to form a system that meets the desired requirements. This new approach of designing is similar to designing a PCB with ICs, thus requiring expertise in “system-design”, and not so much in SoC IC design. Chiplet-based systems inherently enable heterogenous integration of different substrate materials and process technologies (Si, InP, GaAs, SiGe, GaN, etc) which is not possible with a monolithic SoC approach, giving advantages needed for today’s electronic systems. Historically, heterogenous integration of these devices has occurred at the chip level, on a package substrate known as multi-chip module (MCM) as shown in figure 2. The drawbacks with the MCM approach are that it introduces bandwidth and latency related performance limitations, as well as increased size, weight, power dissipation, and assembly costs.
Figure 2. Historical MCM approach of integration.
How will chiplet-based systems help the industry?
First, they can reduce the costs of a system. The SoC approach can quickly become cost prohibitive at advance process nodes, such as at 7nm, especially if the chip is large because it includes analog circuitry and large power I/Os that don’t scale with process technology. This problem is easily avoided with chiplet-based systems by partitioning the circuitry into separate chiplet functions, each optimized for their own functionality and process technology, which minimizes the chiplet size, improves yield, and cuts costs. Moreover, chiplet-based systems can also reduce development and verification costs by using known good die.
Second, chiplet-based systems can enable companies to design high-performance solutions in markets with moderate annual unit volumes. In the past, the only companies that can really afford SoCs are those that are in markets with huge volumes (such as cell phones) or have high price points. But for many markets, products may not be in big enough volumes to pay for the mask costs of an SoC. For those parts of the market working in smaller volumes, chiplets + interposers are an attractive approach.
A third major benefit of chiplet-based systems, as alluded with known good dies, is faster time to market compared to developing an SoC from scratch. Having a product out sooner increases your company’s revenue potential as well as gaining market share and a competitive edge, especially if you are the first to market. There are also many other advantages to using a chiplet-based system such as IP reuse, design flexibility, low-cost customization, design distribution, and many others making this an attractive approach for system companies.
Figure 3. Cadence Sigrity SystemSI power-aware signal integrity analysis
A key part to making chiplet-based systems successful is ensuring the interposer and package is designed correctly. These interposers are going to be filled with multiple high-speed signals, clocks, data buses, and address lanes making signal and power integrity analysis a requirement for proper operation. This is where Cadence’s Sigrity tools can help you with signal integrity analysis, power integrity analysis, and extraction of the interposer and package designs for first time success. A huge advantage of using Sigrity tools is that it includes power-aware extraction and analysis which is essential for getting correct results in these tightly packed chiplet-based systems where signal reflections, cross talk, and simultaneously switching noise can easily be impacted by the power and ground impedances in the PDN of the interposer. Please take a look at our solutions as Cadence is poised and ready to support you in this new era of chiplet-based systems design.