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A major challenge for PCB design teams is how to assure on schedule signoff without driving the designers crazy to design -> route -> re-route over and over again as signal integrity engineers find problems and request changes late in the design cycle. It is frustrating for everyone when an SI expert must raise a red flag when spotting basic reflection-related SI issues, such as improper route topology, missing termination, overshoot, ringback, or extended settling delays. Especially, when the expert knows these basic problems could have been caught much earlier.
Finding a problem late means the design team has a lot of extra work since they've already invested time in routing the design. PCB designers have no choice but to rip up and re-route everything all over again like a hamster running in the wheel. After the PCB designers have completed the re-route, they kick the ball back to SI experts to run another pass of SI analysis and keep their fingers crossed, hoping nothing has broken during the last modification of the PCB design.
The SI expert takes no pleasure in re-running basic SI simulations. Not only do they have to deliver the bad news to their PCB designers again and again, but this takes away from performing the detailed power-aware SI analysis that requires their true expertise.
But wait! Is there any solution to this route-analyze-repeat vicious cycle? What if you could find all the basic signal integrity problems before a PCB is even routed!
Instead of using traditional “ratsnest” connections with Manhattan-route distance transmission lines, transmission line lengths are based on route planning and are much more realistic. In addition, the actual design intent of the topology (daisy chain, star, fly-by) is used. By adding SI analysis to the flow, planning reasonably accurate board level pre-route analysis can detect most types of signal integrity problems earlier in the design cycle.
This solution provides PCB designers the opportunity to make placement edits that would be much more painful after spending time on routing. PCB designers can also save a lot of effort if they need to add any more terminators while there is still plenty of space before routing. By incorporating this pre-route functionality into a design methodology, many signal integrity problems can be found and resolved early. With these basic SI problems resolved, SI engineers/experts will have more time to investigate possible crosstalk and SSN problems when the design is fully routed.
Here is a tech tip video to demonstrate the solution further (the tool demonstrated is Allegro Sigrity SI Base):
Feel free to leave comments below, we are open to all kinds of discussions.