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As signal integrity engineers, we know adaptive equalization is used in today’s multi-gigabit serial links to combat the effects of inter-symbol interference (ISI) due to a bandlimited channel. But how are we currently simulating this, especially in high-speed links like PCI Express Gen 3, Gen 4, and 10GBASE-KR, where backchannel training is actually being used in the hardware to adapt the SerDes transmitter (Tx) in concert with receiver (Rx) equalizer settings?
Most likely we have been using IBIS-AMI models to automatically adapt the Rx equalizer settings while manually sweeping the Tx equalizer settings to try to find the best bit-error rate (BER), given the current simulator limitations.
What are your thoughts about this simulation approach for high-speed links that really use backchannel training? Well, it is probably the best we can do with the available simulation tools but there are certainly at least three big issues with this approach.
First, manual sweeping of the Tx equalizer settings is really time consuming. And if you want to also sweep some of the interconnect channel parameters too, the combinations explode very quickly. With today’s tight product development schedules, we don’t have time to simulate all possible combinations and would need to settle on a solution that satisfies both our BER requirements as well as our schedule requirements.
Second, this “satisfactory” equalizer setting is not likely going to be the optimal equalizer setting for your system. A satisfactory setting may be sufficient to meet the BER requirements, but the optimal equalizer setting gives us the greatest design margin and the most flexibility. This extra design margin redistributes the signal integrity trade-offs more in our favor allowing us additional flexibility to make routing changes, alter component placements, and make other system changes that can lead to smaller boards, less cost, and even faster time-to-market products.
Finally, the third issue with the current simulation approach is that it just doesn’t represent how the actual SerDes hardware works. The whole point of IBIS-AMI modeling is to allow simulation to emulate the equalization behavior of the actual hardware, and backchannel training is a major aspect of that, and can significantly impact the BER of the system. Backchannel training accomplishes this by adapting the Rx and Tx equalizers in combination, which produces better BER margins than adapting them individually.
Here is the good news, recent enhancements to the upcoming IBIS standard, with a target release in the spring of 2018, will support backchannel training. Cadence has implemented early support for this functionality based on both internal and external customer requests and it is currently available in the latest release of SigrityTM SystemSITM .
Signal Integrity engineers will now have the ability to incorporate backchannel algorithms into their IBIS-AMI models, automating the optimization of Tx and Rx equalization settings in the same manner as their actual SerDes hardware devices. This saves significant time while also allowing signal integrity engineers the possibility to improve their multi-gigabit serial link design with the extra design margin obtained from backchannel simulations.
For more details, please attend the DesignCon paper "Backchannel Modeling and Simulation Using Recent Enhancements to the IBIS Standard" presented by Ken Willis from Cadence Design Systems on Thursday, February 1st, at 10:00am. Also, don’t forget to attend Cadence’s free sponsored technical paper session on Thursday February 1st at the Great America 3 Room. And last but not least, Team Sigrity will be at the Cadence exhibitor booth all week during DesignCon to help you with any design, analysis, or simulation challenges you may have. We are looking forward to seeing you soon at DesignCon 2018!