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Here are three graphs that clearly show you the differences:
Graph 1: NRZ, waveform, eye diagram
Graph 2: PAM-3, waveform, eye diagram
Graph 3: PAM-4, waveform, eye diagram
When signaling moved from parallel to serial for high speed connectivity, the timing challenges were removed from the PCB and clock and data recovery became the responsibility of the silicon. Now that 16 Gbps serial links are becoming common (i.e. PCIe 4.0), it appears that we may not be able to double the speeds of next generation interfaces without doing something creative. OIF-CEI is currently specifying interfaces at 56 Gbps that include 2 bits per unit interval. This multi-level signaling is referred to as PAM-4.
Another application of multi-level signaling is seen in automotive Ethernet. In this case, the 100 mbps signaling is much slower than OIF-CEI interfaces, but by including more than one bit per transition, the rise time of the signals can be slower which will typically produce less EMI, which is an important safety consideration in passenger vehicles. The automotive Ethernet standard, 100-Base T1, uses PAM-3 signaling which transfers 1½ bits per unit interval.
So, whether you are looking at OIF-CEI or automotive Ethernet, one thing to think about is validating that the PAM encoded signals are compliant with the standard before bringing a prototype to the lab. Cadence Sigrity signal integrity technology currently supports PAM-3 and PAM4 signaling so that you can simulate how the signals will behave as they travel from transceiver to transceiver.
To understand the PAM signal and analysis technology better, here is a short educational video to demonstrate the topic further. It might help you to successfully design and analyze PAM encoded serial link interfaces:
Feel free to leave comments below, we are open to all kinds of discussions.
(Tool demonstrated is from Allegro® Sigrity™ System Serial Link Analysis Option)
Addressing the Challenges of Serial Link Design and Analysis