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With initial PCB trace and via models in place for our hypothetical PCI Express Gen 4 serial link, the remaining missing piece is for an IBIS-AMI model of the transmitter, with “AMI” standing for Algorithmic Model Interface. As the name implies, an IBIS-AMI model has a “circuit” part, which is defined in traditional IBIS (I/O Buffer Information Specification) format, and an “algorithmic” part, defined in AMI format. Both are required for the complete model.
The circuit, or IBIS part of the model is used to describe the transmitter’s voltage swing, output impedance, parasitics, and rise/fall time characteristics. This information should be in the data sheet for your SerDes transmitter. Assume that the data sheet shows that the swing is around 1V differential into 50 ohm loads, with a single-ended 50 ohm output impedance, pad capacitance in the 0.5pF range, and single-ended rise/fall times around 20ps. This is fairly straightforward to put into a standard IBIS model as a starting point.
Figure 6 – Preliminary IBIS model
The algorithmic, or AMI part of the model is used to describe the equalization behavior of the transmitter. In the case of PCI Express Gen 4, this consists of Feed Forward Equalization (FFE), or “de-emphasis”. FFE will contain multiple “taps” that represent the main and boost drivers that produce the de-emphasis behavior, boosting transition bits (ex. 0 to 1 transition) and de-emphasizing steady state bits (ex. multiple 1’s in a row). The strength of these taps are usually described in terms of coefficients, that show their scale as compared to the main tap.
Figure 7 – FFE and transmitter waveforms, with PCI Express presets
IBIS-AMI simulation tools today often include utilities to generate AMI models directly, taking the information described above as input. Again, this information can typically be found in the data sheet for the SerDes transmitter. Assuming that the transmitter of interest uses similar de-emphasis settings to those described in the PCI Express specification, the tap coefficients shown above can quickly be used to directly generate an AMI model, using automated utilities as described earlier.
Next time > Enabling Constraint-Driven Design
Ken Willis is a Product Engineering Architect focusing on SI solutions at Cadence Design Systems. He has nearly 30 years of experience in the modeling, analysis, design, and fabrication of high-speed digital circuits. Prior to Cadence, Ken held engineering, technical marketing, and management positions with the Tyco Printed Circuit Group, Compaq Computers, Sirocco Systems, Sycamore Networks, and Sigrity.
More about Signal Integrity:
How to Address the Challenges of Serial Link Design and Analysis
Why SerDes Signaling Is Trending Towards PAM Encoded Signals
How to Build an IBIS-AMI Model (Video)