• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Blogs
  2. Whiteboard Wednesdays
  3. Whiteboard Wednesdays - Verification Challenges for SoCs…
References4U
References4U

Community Member

Blog Activity
Options
  • Subscribe by email
  • More
  • Cancel
Whiteboard Wednesdays
SoC
PCI Express
verification

Whiteboard Wednesdays - Verification Challenges for SoCs Integrating PCI Express Subsystem IP

16 Jan 2018 • Less than one minute read

In this week's Whiteboard Wednesdays video, Nick Heaton, Distinguished Engineer, Cadence, describes the verification challenges for SoCs when integrating PCI Express subsystem IP.

Attachment:

  • wbw-nick-heaton.jpg
  • View
  • Hide

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information