• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Blogs
  2. Whiteboard Wednesdays
  3. Whiteboard Wednesdays - A Standard Approach to Lane Margining…
References4U
References4U

Community Member

Blog Activity
Options
  • Subscribe by email
  • More
  • Cancel
Whiteboard Wednesdays
PCIe Gen4
PCIe
PCI Express

Whiteboard Wednesdays - A Standard Approach to Lane Margining as Defined by PCIe 4.0

11 Jul 2017 • Less than one minute read

In this week's Whiteboard Wednesdays video, IP Architect Gopi Krishnamurthy explains the lane margining requirements of the PCI Express 4.0 specification.  This spec standardized the previously ad hoc approaches to measuring lane performance in the face of crosstalk, reflection, and jitter caused by process, voltage, and temperature variations.

Attachment:

  • wbw-gopi-k.jpg
  • View
  • Hide

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information