Home
  • Products
  • Solutions
  • Support
  • Company
  • Products
  • Solutions
  • Support
  • Company
Community Blogs Whiteboard Wednesdays Whiteboard Wednesdays - Closing the Memory Wall Gap

Author

References4U
References4U

Community Member

Blog Activity
Options
  • Subscriptions

    Never miss a story from Whiteboard Wednesdays. Subscribe for in-depth analysis and articles.

    Subscribe by email
  • More
  • Cancel
Design IP
2D Memory
Memory
DDR4
3D memory
wide i/o
HMC
HBM
UFS
eMMC
Tensilica
DDR4 3DS

Whiteboard Wednesdays - Closing the Memory Wall Gap

21 Jan 2014 • Less than one minute read

We're excited to introduce Whiteboard Wednesdays, a new video blog series that will shed some light and provide some practical insights on how to address a variety of intellectual property (IP-) related design challenges. Our inaugural segment addresses the memory wall gap--that phenomenon that occurs when the bandwidth of microprocessors outpaces the bandwidth of the memory in the design, degrading system performance. 

Watch our first Whiteboard Wednesdays episode, where Cadence's Scott Jacobson takes a closer look at how CPU performance outstrips memory transfers and the options available to system designers. He also covers 2D solutions like EMMC 5.0, UFS, and DDR4, as well as 3D solutions like HMC, HBM, Wide I/O2, and DDR4 3DS.

We hope you find this series to be helpful. We also welcome your feedback. Share your ideas for future episodes and any other comments or questions in the Comments area under this blog post.  


© 2023 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information