Whiteboard Wednesdays - The Evolution of NAND Flash - Whiteboard Wednesdays - Cadence Blogs

Whiteboard Wednesdays - The Evolution of NAND Flash

In this week's Whiteboard Wednesdays, Lou Ternullo explains NAND Flash and the need for advanced error correction. Lou also details the Berlekamp Chaudhuri Hocquenghem (BCH) algorithm. Learn how this algorithm is implemented and how engineers are using it in their designs today.

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ternullo

Hi. thanks for your question. Your understanding is correct. MLC stands for Multi-Level-Cell and TLC for Tri-Level_cell. SLC devices support a single data state per cell, MLC devices support 2 data states per cell and TLC support three data states per cell. The easiest way to look at it is that even though you can support more storage bits per cell and thus increase the effective density of the NAND device, the signal margin in to sense the data state in the NAND cell will be reduced. simplistically for MLC the signal level will be reduced in 1/2 and for TLC devices the signal level will be reduced by 1/3. the reduced signal means there is less statistical margin to reliably sense the correct data state which could lead to higher bit failure rates. As with most things there are trade offs in selecting a NAND flash device. MLC and TLC provide higher density, but the number of supported programming and erase cycles are significantly reduced. I hope this helps to answer your question. The following link should help provide some additional information on the differences between SLC and MLC NAND devices. www.micron.com/.../choosing-the-right-nand Thanks again for your question. Lou
Anonymous

Nice Intro Lou. I got lost a bit when you described how SLC, MLC, TLC increasingly need more error correction . Are you saying that TLC is more prone to error vs. SLC so a higher number of ECC bits and codeword is required? Do standards like 26262 play a role in making memories more robust and how is that affecting NAND flash design?

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Whiteboard Wednesdays - The Evolution of NAND Flash

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