Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
On the connector shown below I want to connect the shapes around the perimeter to the internal gnd layer. I have selected each shape and assigned the net "gnd" to each but I get no ratsnest showing a connection needs to be made. The status command does not show them as unconnected either.
Previously I would have edited the copper area to assign the net, then placed a "free via" to connect to the gnd plane. I don't see a method to get a small hole into the shape.
I tried to add pins to the library part, but that requires adding additional pins to the schematic symbol. Plus, can you even have a pin inside a shape?
(I sure picked the right avatar........)
It looks like your shapes may be static shapes. You may need to change them to dynamic shapes before you can associate them with nets. Select the shape and RMB - Change shape type
In reply to budnoel:
Tried that. When I try to change the shape type I get "A shape that is part of a symbol cannot be changed".
When I try to edit it in the symbol editor, the option to change the shape is greyed out and only the defer dynamic fill is available. (Don't know what that does........)
In reply to TH Designs:
It sounds like you may have simply drawn the shapes in symbol editor. I believe you need to create padstacks for those odd shapes if that is indeed what you want your lands to look like. If you do a File - New and choose "shape symbol" you will be able to create the shape in editor. You then need to create a new padstack in padstack designer. You can associate the shape you created by choosing under the Layers tab "Geometry - Shape" and then browse to the shape. Let me know how you make out.
In the board editor:
In reply to fxffxf:
I did exactly what you suggested by selecting the shape then assigning the net from the options box where the list of nets are available. If I hover ofer the shape it tells me that the net I chose is what the shape is associated with BUT, there is no rats nest and no way to route the net to the inner layer.
I have experimented with modifying the library symbol to have a pin in each of the shape areas. I then edited the schematic symbol to add these pins as power pins, named GND with no length so they don't show on the part.
When I load the netlist, the symbol is updated, but it is no longer placed or routed. I then tried refreshing the symbol on the board without loading the new netlist, but it won't let me because the number of pins don't match the netlist. Thought if I could get the part loaded, then bring the netlist over everybody would be happy. No can do.........
There has to be an easy way to connect shapes of a symbol to a net without having to reload the parts and re-route everything.
Ratsnest are not displayed to shapes. There is an Isolated shape report that you can acccess via the Reports or Status dialog. If the shape is isolated then you will need to tie it to the appropriate net by via routing from the shape to an object on that net. If could just mean that you need to add a via from shape to another layer to tie it to a already connected shape. This can be done via the add connect command.
This assumes you are using positive planes.
Maybe this is how it is done, maybe I just stumbled onto something.......
After I assign the 10 shapes around the connector to the "GND" net, I was expecting to see a ratsnest that I could clikc on and route from. Didn't have one. Since I have spent close to three hour on this, my frustration level is climbing so I just tried Route - Connect, clicked on the shape and made a short trace, double clicked to insert a via and the connection was made to the GND plane!
I tried the same thing on a shape that did not have any net associated with it. It allowed me to route a trace and place a via, but no connection was made to either plane (which I would expect).
So it looks like assigning the shape to a net and the MANUALLY putting in a trace from the shape to a via will connect it to the gnd plane. (I would really like the via in the shape, I'll try that also)
I don't know if this will remain when a new netlist is loaded, but I'm hoping it stays.
fxffxfRatsnest are not displayed to shapes. There is an Isolated shape report that you can acccess via the Reports or Status dialog. If the shape is isolated then you will need to tie it to the appropriate net by via routing from the shape to an object on that net. If could just mean that you need to add a via from shape to another layer to tie it to a already connected shape. This can be done via the add connect command.This assumes you are using positive planes.
Looks like we were typing at the same time................ You stated what I think I figured out. Thanks!
Tom on those connectors that have mounts, you might want to think about making the pads as an actual padstack, i.e adding a pin for each one. On the schematic side you can either hide those pins or re-draw the symbol to include them.
My preference is one from electrical/drc checking. Thing is the symbol might not look ideal on the schematic but doing those mounting pads as pins has the added advantage that your schematic will exactly match that board, plus you will also get a net.
I think having floating pads in a footprint can lead to errors on the board, sometimes costly ones.
Anyway just a suggestion.
In reply to ScottCad:
In the future I will do that. I made a new symbol already. I would have done it on this board, but every way I tried, when I brought the netlist in it blew away my routing / placement. I didn't want to have to re-route 8 connectors again so for now I am editing the shape in Editor and assigning it to the gnd net, then manually placing a trace/via to gnd. It works pretty well with no DRC's. I even reloaded the netlist a few times and it didn't impact what I did.
I'm probably jinxing myself here, but I think I'm getting the hang of this monster. This board was a pretty simple 4 layer debug board for a video controller. I start a job next week which will be the real test of what I have learned (or haven't learned). 12 circuits of high current DC, processors and MOSFETS. Not to mention the heat dissipation issues that go along with such circuits. I expect it will take about 30% longer then I estimated due to the learning curve I'm still on. I'm looking forward to it, in a sort of demented way..........
Have a great weekend!
Tom, not sure if you spotted it but there is an option in capture and also in Import Logic to leave existing etch alone when doing a forward annotation. That sucker is handy if you have routes routed in and you dont want them to be blown away.
When you netlist in capture you could un-check "Allow etch removal during eco"
Best of luck on that new board, sounds like you are ready to take the Bull by the Horns : )
Have a nice weekend too