I am creating a pcb with multiple srams connected to an FPGA on 1 data bus. I intend to clock the srams and the fpga at 150 MHz. I am concerned about what issues will arise when connecting mutliple srams to the same data bus (only 1 sram will have its output enabled at a time). For example should I worry about impedance matching each branch of the bus, will enabling and disabling the outputs of the SRAM's cause strange transients on the entire bus, will having the bus split cause loop currents to form, or anything else I can't think of?
May I suggest you post this question in the "Logic Design" forum? You might get better respone in that forum.