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Has anybody tried the via modelling in SI. I am interested in changing the RLC of via in sigxp...is it possible, can anybody explain me on this...License-SI XL.
Also probing of topology, is it possbile or necessary to see the response of the toplogy at different instant.. as per my knowledge the respone should be from pin 2 pin......is it right...
Allegro SI has the ability to allow you to look at the via model and change the specifics. Go to Analyze > Library > double click on the .IML file > change type to Via > click on Edit button. This will launch Via Model Generator which may be used. If you click on Text Edit button then a text editor is launched which shows the spice ckt content of the via in question which may be modified.
To probe a topology at a location other than the driver or receives you may add a dummy probe. It's in one of the Cadence supplied library files. Add by going to Edit > Add Part.
In reply to Khurana:
i got it... isn`t possible to get the information of RLC values of pads as we get RLC values of net using show parasitics cmd..