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I've done some searching through the forum but haven't found the answer I'm looking for. I would appreciate if anyone can suggest some solutions to my situation.
Essentially I am trying to define some relative propagation delays for a PCI bus and would like some advice. I am using the properties editor in OrCAD Capture CIS to define my constraints. The system is set up as follows:
- There are 2 IC's on the board which are on the PCI bus. The PCI bus is entering the board from a common connector.
- Each IC shares all common PCI signals except for clocks (i.e.: nets on the bus have multiple pin pairs except for clocks). A PCI bridge is driving all clocks from a secondary board and hence there is a distinct clock for each IC.
Let's assume that IC "A" is paired with clock "A" and IC "B" is paired with clock "B". The PCI bus routes from the connector, through IC "A", and then to IC "B". This is what I would like to do:
1) Match the length of the PCI bus going to IC "A" with the length of the trace of clock "A".
2) Match the length of the PCI bus going to IC "B" with the length of the trace of clock "B".
My initial try was to define a propagation delay for each of the clock lines and then set each of them up as a target for relative propagation. I then attempted matching pin pairs with the clocks. This doesn't work for me as it seems, to me, that you cannot assign different pin pairs from the same net to different matched groups.
Any help or suggestions is much appreciated.
I think you're on the right track. Perhaps you might want to match differently... that's for a later exercise. But if I read what you're saying you want, you should do the pin pairs like you state. Did you enable the mode that checks relative propagation? It defaults to off....
So I have created a test project to see if we're on the right track. Take a look. It is just for a reality check....no real symbols were harmed in the creation. I think it gets the message across.
With this as a template, let me know what works/doesn't work.
You can do this in OrCAD Capture v15.2 or higher. Select the nets > right click > select Properties > go to Flat Nets tab > left click in Relative Propagation Delay tab > right click > Invoke UI (or something like that). This will pop up Relative Propagation Delay window. You can create the rule there by specifying the pin pair and delta/tolerance values. Then, you can copy and paste the property value to other cells for the nets in the match group. There should be a video on this - search for this in OrCAD Capture Help.
You might also want to look at a tool named MakeCAP - more info at http://www.ema-eda.com/products/other/makecap.aspx. The tool bolts on to OrCAD Capture and gives you the ability to create/assign high speed properties for Allegro PCB Editor.
In reply to redwire:
Thanks for the input. As an FYI, I only have OrCAD capture CIS installed on my system, not Allegro. Our board designs are contracted out which is why I'm trying to define my delays in CIS.
In any event, I used a viewer to take a look at your template and the dummy layout is exactly my situation. Let's move to some syntax and see if we can iron out some proper propagation delays. Let's use J1, U2 and U3 as in your dummy layout.
First off, I define some propagation delays for each clock. Let's assume the clocks are connected as J1-1 to U2-1 and J1-2 to U3-1. My constraint is that each clock could be a minimum of 0.5" and a maximum of 4".
PROPAGATION_DELAY (CLK1) = J1.1:U2.1:500 mils:4000 mils
PROPAGATION_DELAY (CLK2) = J1.2:U3.1:500 mils:4000 mils
Let's now define the clocks as targets for matching:
RELATIVE_PROPAGATION_DELAY (CLK1) = PCI_CLK1:G:J1.1:U2.1::
RELATIVE_PROPAGATION_DELAY (CLK2) = PCI_CLK2:G:J1.1:U3.1::
Now let's take, as an example, PCI data/address line 0 (net name = PAD_0). Let's assume that it's connected from J1-3 to U2-2 and U3-2. Net PAD_0 has two pin pairs; J1-3 to U2-2 and J1-3 to U3-2.
This is the point where I would like to create some relative propagation delays using each clock as a target. To do this I would have to have net PAD_0 included in both matched group PCI_CLK1 and PCI_CLK2. I can't seem to do this.
Can you comment any further? Am I not defining things the right way?
In reply to BumblebeeTuna:
I don't know what level license you have for OrCAD but I can not (never have) been able to set up the constraints you're doing in OrCAD. I use Allegro exclusively for that. But what you are asking for is AOK. The CM in Allegro allows pin pairs to include the same pin multiple times for pin pairs. I changed the setup (like I was hinting at in the last post) to what I think you're asking for.
Take a look at the net_constraints.txt file in my zip and you can see a text view of the setup I have to meet the conditions you're asking for.
When I backannotate to OrCAD it pushes only the rel propagation property back to the clocks since it's not on a pin-pair.
See if this is what you desire -- not sure how you enforce constraints from OrCAD with your 3rd party layout. It's all internal here and Allegro is the central control point for constraints.
Ping back if you have more questions after looking at the files I sent
I took a look at the constraints.txt file and that's exactly how I want to set up my constraints. I'll have to contact support or perhaps hear from someone else on the forums as to whether I can actually do this in Capture rather than Allegro.
Thanks for the help, it's much appreciated.
You may create a pin pair in OrCAD Capture and have it included in a match group (lets say the name of the match group is MG1) so the syntax would be something like MG1:G:U1.15:U2.8:0 mils:100 mils, however OrCAD Capture is not equipped to let you assign the same pair so that it's part of another match group. This is doable in Allegro but not in OrCAD Capture (in Capture, a pin pair can be part of a single match group at any given time - I am pretty sure). In MakeCAP, a pin pair may belong to 2 or more match groups.
In reply to Khurana:
Thanks Khurana. I'll check out MakeCAP.
Both Capture, CIS and Allegro all support identical Allegro Properties. While the syntax may be complex, a PinPair can be in many Matched Groups, especially driven by Capture/CIS into Allegro. MakeCAP will make the creation of the Property syntax much easierbutthe PinPair/Match Group definition capability is intrinsic to Capture/CIS.
In reply to daviddfm:
Do you have an example of how you would enter in the syntax for different pin pairs from the same net into separate matched groups?
Glad you asked -
MG1:G:U1.H4:U15.9:0:100 mil:MG2:G:U1.H4:U15.9::100 mil:MG3:G:U1.H4:U15.9:0 mil:100 mil
All for the same Net and same PinPair on the same Net in three Match Groups.
I tried that sort of syntax but unfortunately Capture spits out "invalid syntax" in my session log.
There's no limitations on how many different PinPairs are from within the same Net in different Match Groups (or XNets - you can drive XNet PinPairs from Capture/CIS into Allegro as well). If you use CIS to drive frontend Properties to your outside source vendors, you can certainly support the full-range of high-speed Allegro Properies and Netlist out to them. The key is that all RelProp relationships for all PinPairs within a Net are described in a single RelProp Property definition for the Net. This is all handled transparently in MakeCAP which is where I generated this example.
What Release of Capture are you on?
Inside Capture CIS you can see a movie demonstration this, do the following
This movie is rather good and shows what you need.