Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
My group and I are trying to build a transformized h-bridge dc-dc converter. I was hoping to model this on spice, but have had no luck so far. First I am trying to use an ideal transformer but do not see how you enter the turns ratio to make it step up at the right ratio. Also I was hoping to try to simulate the PWM using the ti494 pwm chip. I know that this chip is still produced by TI, but cannot seem to find the model in Pspice. I am using Orcad Capture CIS. Can this be found in one of the libraries on p-spice. If so what is it called. If this part is not able to be used on this software is there any other parts that would work for my h-bridge simulation. Thanks in advance for any help. Don't know if this is needed but the mosfets on the primary side are MbreakN and all the diodes used are D1N3940.
Ideal, linear transformers in SPICE use a ratio of Inductance, not turns. You could go the linear route, or use the default Kbreak from the Breakout library to couple with a turns ration, the default parameters will require some considerable drive to saturate so, to all intents, this will behave as a linear transformer for smaller loads.
There is a TL493 in the PSpice swit_reg library, this is a close relative of the TL494, the Current Amplifier of the TL493 would need to be tweaked to match the Error1 Amplifier to provide the Error2 Amplifier function for the TL494. Probably best to copy the swit_reg.lib to your own location and rename the LIB file and TL493 model within to ensure that your defintion gets used, the Implementation will need to be changed for the Capture part to pick up your model name for the modified model, also rename a copy of the Capture part to avoid confusion between the models.