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Hi, I am doing a high density connector footprint. It has 100 pins. In my layout, I need 4 this type of connector. I add VIA to each pin of footprint.When I place this part, it gives me 100 errors~ of course each pin has 1 error~LOL
My question is:
First,How to view DRC error message,since it only show 100 errors? I know the capture will shows where has error and also shows reason for that error~Solved
Secondly, When I add etch to footprint, will it cover by silkscreen?
Third, how to change and clear this error ? I add 100 vias next to 100 pins, on dra file. It looks like here is the error come from
You can view DRC errors list using Display----->Status ------>DRC errors (click on the small window present on left side of DRC error).
You can clear the errors by changing the spacing Constraint value into the actual values on the constraint manager(type cmgr on command bar ).for more iformation check the image attached.
In reply to PRASH36:
Thanks for you reply~I find the DRC windows. Thank you so much
But, still meet the same problem. I want make a footprint with a through hole via~then, that will be much easier for layout .
The left side is my original footprint, the right side is what I want.
In reply to Leeya:
The DRC error shown in the image seems to be PAD to LINE error .
decrease the Thru Via to line spacing value and Thru Pin to line spacing value.
Please reffer the image attached .
I do that , still the same very interesting~~Thank you very much
I think this error happens when I made the footprint~~I add through hole pad and etch to footprint file(dra),
Please send me the snapshot of the imformation regarding that drc ....(Display---->Element----->Click on that drc and snd me tat snapshot)
I want the snapshot as in attached image.....Pls find the image attached
I think that error is coming because your pin is not assigned to any net,and this might be corrected after importing the component to the board.
You give some values in the constraints value field as shown in the image and try once,but am not sure its working or not....
Indeed this is a footprint, there is another footprint next to it, and it doesn't have any DRC issue.
I believe there is a problem when I make footprint with 100 vias, but I don't know where and why
Thanks for you replay~~
Don't worry too much about DRC's at the footprint level. Pins, vias and etch have no intelligence at that level, so you may or may not have DRC's, depending on the order you place the items. Once the footprint is placed in on a board, the etch and vias will assume the name of the pin they are attached to, and depending on your constraints, the DRC's will go away.
In reply to chads108:
I generally fix that problem. But I am facing another problem.
It still shows VL error. What confuse me is they happens randem.
In my design, I have 4 of 100 pin connectors. One connector does not have any error at all, another one has two error.
It appears the via is getting assigned to a different net, or none at all. Can you query the via to see what net it is assigned to, if any. You also might try running Update DRC to see if it is something that just hasn't been cleared. Additionally, you could double check your footprint to make sure the via is attached to the cline for each pin, or at least the ones that are giving you the problems.