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I am a Product Manager with Valor Computerized Systems, working closely with Cadence, and am trying to get information from the Allegro user base.
I have received a request from a Cadence Allegro user to support embedded passives in the Allegro-Valor ODB++ interface, and I would like to hear from other Allegro users that are designing pcb's with embedded passive content, or considering such designs in the future.
It is my understanding that although Allegro doesn't 'officially'
support embedded passives, and there are no internal guidelines, it is such a flexible PCB design tool that there are users who are creating such designs, and that one user has written a process for Allegro users.
The link to this process is:
Because each user could implement embedded passive support in different ways it may be difficult to implement Allegro ODB++ support. Therefore I would like to hear from interested users and perhaps explore the feasibility of adopting a generic design guideline.
I am currently trying to implement the burried resistor technology in
my allegro design utilizing the documentation as you listed
I have been unsuccssful at creating an allegro symbol now matter wehter
I use the negative or positive type. See atrtachments
I am on release 15.2
duh the attachment
Drew thanks for the clue, I have used embedded passives before and was
aware of the multiple fiilm layers to produce the one one burried
resistor layer, none of this was the problem the problem was everytime
I went to do a save or create the psm the symbol editor would crash. I
went back to 14.2 and succesfully created the part then upreved now all
is fine with allegro.
Hi Paul,I've used embedded R's for stub termination, but prefer pushing the case for SMT or surface pad interconnects with a mix of blind/buried/stacked via.However there are instances with RF and microwave, where defining inner layer features for symbols would be highly desirous - mostly voids but could be copper. This is where support for embedded would be really useful. A simple example would be controlling the E/H coupling between a series coupling capacitor and underlying return path planes.
Hi. I am using 15.0 and my symbols do not crash, but there has to be a better way to define( or pre-define) the padstacks for buried passives. Any help here?
I'm not sure what your refering to with what your problem is with the
pad stack. But our problem here was that to build the symbol with the
pad burried on an inner layer you had to build the crosss section in
the symbol which did 2 things that are a big problem. One it could not
be put in a global or site library as stackups are independent to
boards, So the part had to stay in a local library.The 2nd obviously is
when the stackup changed so did the sysmbol and padstack had to change
so as with most things related to stackups in cadence there was
duplication of effort! See attached symbol
That's kinda what I meant. There should be an easier method for buried symbols so that one could "assign" a specific llayer for a pad AFTER it is placed......... Or am I asking too much?