Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
How does the Shape's Clearance work for PTH and Non-PTH?For example, I have two though hole, one is plated, the other is non-plated:Unit:mm Plating: Drill: Top Pad: Top Anti Pad:Pad1: Plated 1 circle1.5 1.9Pad2: Non-Plated 1 circle 1 (unuseful) 3.0 Now, there is a Net Shape arround them, the shape has a Net Spacing Type property with 0.15mm(6mil) for Shape to Pin.If the Clearance setting sets Thru pin: DRC and Oversize value:0. The radius of Void around Pad1 is equal to 0.9mm(0.5+0.25+0.15), that means the spacing between Shape and drill edge is 0.4mm. The spacing to pad edge is 0.15mm. For Pad2. the radius of Void is 0.65mm and spacing to drill is 0.15mm.If use the setting:Thru pin: Thermal/anti and Oversize value:0. The Void radius arround Pad1 is 0.95mm. The spacing to drill is 0.45mm, And spacing to pad edge is 0.2mm. For Pad2 void radius is 1.5mm. The spacing is and 1mm.Now, my problem is:When I use DRC clearance, the spacing for Non-Plated pad is not correct. and use Thermal/anti, the spacing for Plated pad is larger than my constraint. I am not sure that my descreption is clear enough. I think it is a problem to deal with the clearance between Shape and PTH/NPTH.BTW, I use SPB15.5.1.
You can do a couple different things to correct this issue. Update your padstacks anti-pads so you get the clearance from edge of hole to edge of copper on both the PTH and NPTH holes that you are looking for and set the Shape Parameters for Thru Pin to Thermal/Anti pad. This could have mixed results if you Net Spacing clearance is greater that the anti-pad provides which will lead to many DRCs.It appears that if you set your Shape Parameters for Thru Pin to DRC that your PTH has the correct clearance but the NPTH does not. One easy to meet your NPTH requirement is to add the Dyn_Clearance_Oversize Pin Property to the NPTH with a value that meets the spacing requirements.I believe the overall fix would be to have the ability to define different Spacing Rule for PTH and NPTH which is not available in the current release of software but I have heard rumors that it is a possible in a future release.Hope this helps,Mike CatramboneUTStarcom, Inc.
Thanks, Mike, I understand your description and solutionNow my solution is familiar with you said. Add a property: Dyn_Clearance_Type=ANTI_THERMAL for all NPTH pads. Then set the shape parameters with Thru pin=DRC But all of these settings are controlled manually. And we should confirm that all the NPTH pads had been selected. I hope all these actions could be easy in the future release.