Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Have you recompiled the design before running the BOM or part manager tool? (Export physical.) That'll do it every time.
Yes Ihave tried to EXPORT PHYSICAL and also expand .. everyway I have. But I couldn't manage to solve. I guess this problem might be an extreme case. I don't know why this happens.Thank you all.
OK, long shot, becasue I don't know how the replace works. Make sure the property you're trying to change is a soft property eg. $LOCATION rather than the hard property LOCATION.Two more courses of action 1/ Delete and re-add the correct part.2/ Raise an SR !!
Thanks for your answers. I have opened an SR for this event but actually they don't pay much attention to that case. And I said OK this one may be an extra case just related to me and they closed the case. Yes you are right I could delete and put a new one but there are more resistors that has the same problem. Actually in the library definition of resistor there are no other tricks or special things defined.Again thank you for your answers.Best regardsAhmet
Hi Ahmet,If you are not happy with the status of the SR with Cadence then please don't let them close it until you have some sort of resolution. In this case Cadence will almost certainly need a testcase to look at the problem - this is by far the best way for them to give you an accurate answer/solution to your problem. One last suggestion - is there an existing pcb layout for this design? I ask this because removing the OPF view may cure this - BUT this is not something that is too be done lightly. The PART_NUMBER property is stored on the schematic (schematic value) and in the OPF (Occurence Property File) which is generally used in hierarchial designs. It looks like the OPF is not being updated with the new PART_NUMBER value. If there's no hierarchy specific properties in the design and a pcb is not yet done then removing the OPF may be an option.I would try this on a archived copy of the design first to see if this resolves the problem - BUT I'll go back to my first statement here, this is something that Cadence can do for you in an SR of they have a testcase to work fromAndy
First of all thank you very much for your suggestions. Yes it worked. I have deleted all the *.opf files in the directory and recompile it and then the problem is solved. The PART_NUMBER property is changed now. We have the PCB board is drawn already but when I compile it (after deleting opfs) I don't use the UPDATE PCB option and backannotating option.
I thought this problem is gonna die with me but it solved:)
Thank you again.
With my best regards