Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
In RTL-Compiler, I used "report power" command after synthesis, and got following report. Could someone please tell me what activity factor and clock frequency are considered by RC to generate that report?
my target clock period was 500ps and timing analysis shows a negetive slack time of -450ps.
============================================================ Generated by: Encounter(r) RTL Compiler v06.20-s027_1 Generated on: Nov 21 2008 01:45:55 PM Module: decoder648 Technology libraries: IO90GPHVT_2V5_3V3_50A_7M2T IO90GPHVT_2V5_50A_7M2T IO90GPHVT_3V3_50A_7M2T IO90GPHVT_ANA_50A_7M2T IO90GPHVT_BASIC_50A_7M2T IO90GPHVT_FILLERCUT_50A_7M2T IO90GPHVT_REF_COMPENSATION_2V5_50A IO90GPHVT_REF_COMPENSATION_3V3_50A PR90M7 CORE90GPSVT CORX90GPSVT CLOCK90GPSVT Operating conditions: wc_0.90V_125C (balanced_tree) Wireload mode: top============================================================ Leakage Internal Net Switching Instance Cells Power(nW) Power(nW) Power(nW) Power(nW) ------------------------------------------------------------------------------------decoder648 480027 567216066.450 1140456537.747 407240261.752 1547696799.500
I believe this is some of the information you are looking for
rc:/> get_attr -h lp*default* * Usage: get_attribute <string> [<object>+] <string>: attribute name [<object>+]: object of interest (must be unique) attribute categories: lp_tcf tim attribute name: lp_default_toggle_percentage category: tim (controls timing optimization and returns timing information) object type: clock access type: read-write data type: fixed point default value: no_value help: Default toggle-rate scale-factor of data signals based on clocks. attribute name: lp_default_probability category: lp_tcf (returns switching activity information) object type: instance access type: read-write data type: fixed point default value: 0.50000 help: Default probability for all nets within the hierarchical instance to be high. attribute name: lp_default_toggle_rate category: lp_tcf (returns switching activity information) object type: instance access type: read-write data type: fixed point default value: 0.02000 units: /ns help: Default signal toggle rate for all nets within the hierarchical instance. attribute name: lp_default_probability category: lp_tcf (returns switching activity information) object type: design access type: read-write data type: fixed point default value: 0.50000 help: Default probability for all nets in current design to be high. attribute name: lp_default_toggle_rate category: lp_tcf (returns switching activity information) object type: design access type: read-write data type: fixed point default value: 0.02000 units: /ns help: Default signal toggle rate for all top level nets in current design. rc:/> get_attr program_version /v08.10-s125_1
Note that I included the RC version I was using since this may have changed in recent release. I strongly encourage you to look at the low power user guide since there is ample information there, not only about what you are asking, but also as to how activity is propagated and other information you may find of value such as looking at power vs. time dynamic activity and other useful low power features.
In reply to grasshopper:
BTW, I meant the RTL Compiler Low Power User Guide
if the default toggle rate is 0.02 (1/ns), then is it changed by only setting clock period? or toggle rate should be set by setting its attribute?
I have a clock period of 500ps and default probability is 0.5 and I didn't tuch toggle rate attribute. In this case can I say that the power is reported for toggle rate of 1/250 ps == 4G, although timing shows a neg. slack time of -450?
In reply to naderi:
the answer to your question is no. toggle activity is independant from clock definitions on SDC. In general, dynamic power analysis with default rates is not terribly accurate. I suggest you use VCD, TCF, or SAIF from simulation to produce more accurate results. VCD is nice in that it allows you to look at time vs. power profile which further enable you to address the block responsible for peak power surges. If you have access to Palladium emulation and power is a hot ticket item for your team, I would certainly inquire about DPA.
PS: Please post RC questions in Logic Design forums. I think you will get more replies there