Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
we are working in a 5 metal layer process with Encounter 5.2. In our design, we have decided to stack the power rings, i.e. the VSS ring is on metal layer 1 and the VDD ring is in the same position but on metal layer 5. However, we are confronted with the following problem during power routing: If the ring's width is greater or equal to 1001 µm (drawing dimensions), the vias from metal 3 to 4 and metal 4 to 5 are missing, so the core rows are not connected to VDD.
However, if the ring is only 1000 µm wide (or less), this problem does not occur. Unfortunately, 1000 µm is by far not enough for our design.
Another interesting thing is that the power stripes (on metal 2) are connected correctly even when their width is greater than 1000 µm. From this we draw the conclusion that this is not a problem related to viarule definitions in our LEF technology files.
Has anybody encountered a similar problem or, even better, can provide us with an explanation of this behaviour?
Thanks in advance!
I was going to do some testing on a design, but I wanted to check first- are you sure you want rings that are one thousand microns wide? That seems massive and sure to violate technology rules that limit how wide a single wire can be without needing to be split or slotted.
Could you confirm this is the intent? What process node is this?
In reply to Robert Dwyer:
thanks a lot for your response. We are working in a process with shrink factor, i.e. the 1000 microns wire will actually be 70 microns wide in final dimensions. The shrink factor was specified using ui_shr_scale in the configuration file. We have thoroughly checked the LEF files as well as the design rule specification documents, there is definitely no rule violated by a wire that is 1000 microns (drawing dimensions) wide. There is also not a single warning to be found in the logs that would indicate a rule violation.
What's more, we made power stripes with a width of more than 1000 microns (just for testing purposes), and they were correctly connected.
However, since we were not able to find a solution to this problem in time, in the end we have indeed split the ring into to two rings, this worked well. So for us, the problem is "solved". Thank you!