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I am using SoC encounter 11.12 with STM65LP designkit to place and route a design. The design is synthesized with and RC 11.21. While the script runs through I find a bunch of warnings within the log, which I cannot really interpret
#WARNING (NRAG-44) Track pitch is too small compared with line-2-via pitch
-> is this crucial ?
**WARN: (ENCCK-6350): Clock net clk__L3_N7 has 47.6131 percent resistance deviation between preRoute resistance (140.469 ohm) and after route resistance (95.1601 ohm) values. This may indicate correlation issues like jogging in routing for this net.
-> What is meant by this ? What is jogging ?
**WARN: (ENCEXT-3518): Lower process node design mode set (using command 'setDesignMode') but technology file for TQRC extraction not specified. Therefore, going for postRoute (effortLevel low) extraction instead of recommended extractor 'TQRC' for lower nodes. Use command 'set_analysis_view/update_rc_corner' to specify technology file for TQRC extraction to take place.
-> Since I have captables and no TQRC file, i can ignore this right ?
**WARN: (SI-2261) Accuracy may not be optimal because no noise libraries have been loaded. To get the most accurate noise analysis, load the noise libraries before the set_noise_run_mode command. To load the noise libraries use the read_lib -cdb command or specify them in the configuration file. [celtic_ndc]**WARN: (SI-2291) Ignoring the timing window data for 24111 nets. These nets will have infinite timing windows. [load_timing]**WARN: (SI-4557) A total number of 1922 nets have no outputs (they are not connected to any receivers and have not been marked as primary outputs); they cannot be analyzed. The nets without outputs are listed prior to this message. [process_netlist]**WARN: (SI-4514) Could not find vdd for analysis [celtic_ndc]**WARN: (SI-4514) Could not find gnd for analysis [celtic_ndc]
Would be glad if someone could clearify this warnings and my questions.
MartenI have been living, breathing and eating STM65LP for the last few years and I must admit I've had my share of nightmares.Slightly different software versions , rc v12 and encounter v10, the STM flow we have installed here will not allow me to use v11's default MMMC setup.WARNING's should be checked into, they MAY cause SIGNOFF problems later. ERROR.s must be solved they WILL cause major problems later.NRAG-44 ignore, to do with the bump redistribution AP layer in ./COLLECT_DATA/TECH/cmos065_7m4x0y2z_AP_Worst.lef .ENCCK-6350 clockDesign predicts clock routing but nanoRoute actually implements the routes. This is just a warning that the prediction differs from the actual, if the CTS results are satisfactory ignore the warning.ENCEXT-3518 ignore, setDesignMode -process 65 defaults to use TQRC, but the STM flow is stuck with older .captable's.I cannot help you with the SI warnings, I wrote my own custom scripts for everything after "gmake step_routing".Come to think of it I pretty much modified / simplified every script before routing as well.The largest problem we had was the lack of correlation between Cadence ENCOUNTER and Synopsys SIGNOFF.Stefano our local Cadence AE was able to write me a new viewDefinition.tcl that brought the two systems inline.If you have problems with SIGNOFF correlation, I may be able to help.Getting close to tapeout of the "Mark 2" Then sleep.Shawn