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I am in the gate level power simulation phase. I have multiple (X100) instances of the same module and I do not want to run all of them as gate level modules just the ones I'm interested in capturing there signals. The only way I know how to do it is during compile time using `define. The problem is that we want to hold a single compiled design and not to have to compile each test again according to the test designer needs.
I would like to know if there is a way to define the instance module type during the simulator initial stages. Maybe SystemVerilog (Which I have no deep knowledge about) have an option to do so. I have tried using the $test$plusargs to differ between the different instances but it does not compile.
hey workman; did you ever find a solutio?