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I want to do assertion check in a "for" loop, and I want to do assertion check in every loop(totally 10 times in my file), but it seems that the assertion check only done once, and at the very beginning of the file instead of after going into the loop. ncsim shows "ncsim: *E, ASRTST (./top.v, 55): (time 0 FS) Assertion top.assert_P1 has failed (1 cycles, starting 0 FS)".
following is my code, Can you help me?
class rand_cov; rand bit[4:0] data_a;endclass
module top; int i; int succ; bit[4:0] data; rand_cov cov_t; initial begin cov_t = new(); for(i=0; i<10; i++) begin $display("NO. %d", i); succ = cov_t.randomize(); data = cov_t.data_a; $display("data = %0d", data); //psl property P1 = always ( !(data == 14) ); //psl assert_P1: assert P1; end endendmodule
There are a couple of things going on here. The most fundamental is that a PSL assertion is a "concurrent" assertion. It runs independently of the HDL code in which is appears. The fact that the comments describing the assertion appear inside an HDL for-loop or initial block don't make any difference. You'll get the exact same behavior if you write:
initial begin cov_t = new(); for(i=0; i<10; i++) begin $display("NO. %d", i); succ = cov_t.randomize(); data = cov_t.data_a; $display("data = %0d", data); end end //psl property P1 = always ( !(data == 14) ); //psl assert_P1: assert P1;
Because a PSL assertion is a "concurrent" assertion, it will decide on its own when to execute. Usually it is after a clock event encoded into the assertion with something like an "@(posedge clk)" clause. This assertion doesn't have any clock defined, so it will default to executing after any change to the "data" signal inside it.
Thirdly, because there is no time involved in the for-loop, the first assignment to data will cause the assert_P1 assertion to schedule itself for evaluation. But then the for-loop continues to make 9 more assignments to data, all in the same time-slot. Since the PSL assertion won't execute until after the for-loop is complete, unless the last assignment to data was "14", the assertion will pass.
If you want the behavior you've coded here, you probably want to use a SystemVerilog "immediate" assertion. This is an HDL statement that executes immediately.
$display("data = %0d", data); assert_P1: assert ( !(data==14) ) else $display("data was 14!");
Or you can add some delay to the for-loop, so that PSL assertion scheduled to execute later in the time-step will have a chance to see the value on data and react to it.
initial begin cov_t = new(); for(i=0; i<10; i++) begin #1 $display("NO. %d", i); succ = cov_t.randomize(); data = cov_t.data_a; $display("data = %0d", data); end end //psl property P1 = always ( !(data == 14) ); //psl assert_P1: assert P1;
In reply to TAM1:
Thank you for your help, you helped a lot.
According to you advise, I think we should put the delay (#1) after "data" is assignment(data = cov_t.data_a), otherwise, the tenth assertion check(i = 9) will not be done.