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I'm currently converting a legacy testbench to use SystemVerilog interfaces between the DUT and some behavioural models. The testbench code includes a specify block that uses the $width system task to check for glitches on a signal between the DUT and one of the models.
I've tried to update the code so that the $width task now checks the equivalent signal within the interface instance, which connects the DUT and the model. For example:
$width(posedge interface_inst.my_signal, 100, 0, my_notifier);
Unfortunately Incisive reported a ncvlog error (ILLHIN) for the line containing the $width task call:
"A hierarchical name was used as an identifier where a hierarchical name is not allowed. Use a simple identifier."
I then moved the specify block to the interface itself, as on reflection, this seems a more suitable place anyway. The specify block is defined within the scope of the interface declaration. For example:
interface my_interface ();
logic my_signal, ...etc
modport ( ...);
$width(posedge my_signal, 100, 0, my_notifier);
This time, Incisive reported a different ncvlog error (DECINM) for the line containing the specify keyword:
"The declaration is only valid within a module, interface, and program and not supported within task, function and package."
The message clearly states that a specify block within an interface is supported so why is Incisive reporting an error?
Thanks in advance for any help.
I have since found out that IEEE Std 1800 (SystemVerilog LRM) does not allow specify blocks to be defined in interfaces.
Also, Incisive does not currently support the use of hierarchical references in specify blocks.