We are using VHDL flavour PSL with a VHDL design, and are seeing assertion failures due to VHDL delta delays.
I read that SystemVerilog has solved this problem by checking all assertions in a new simulation phase. Is there any way of forcing ncsim to do this for a VHDL design?
I think from the silence so far you can pretty much infer the answer the answer to your question. The PSL assertion language does not specify when it executes and thus is subject to delta-cycle types of race conditions. There is no easy way to force the simulator to use any particular cycle for its evaluations.Selecting an early or late clock edge for the assertion is really the only control that you have.