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I have a traditional testbench that instantiates a Stimulus Generator and a DUT. Looks like this
//in module tb.v
The stimulus generation occurs within the driver.
I would like to add an UVM Environment with only a Monitor, Scoreboard and Functional Coverage to this testbench. I created a wrapper called "svid_packet_monitor" and instantiated that in the tb.
I am new to the whole UVM thing and am not sure how the code inside the monitor wrapper should look like. I took a first stab at creating a package with the monitor and associated class items and imported this inside the svid_packet_mon_wrapper. Then I created my_test inside the wrapper that extends uvm_test but I am not sure how to start this up. I am attaching the code for the monitor package and the monitor wrapper( with questions inside the monitor_wrapper code ). Any help to put this together would be highly appreciated...
Hello! I Just found this thread now. I'm having a problem that is very similar to this one.
We already have a non-UVM SystemC verification environment to verify certain DUV, but this environment lacks in coverage. We want to use a UVM agent (with monitor and coverage collector) with this environment so we can track what is beeing sent to the DUV.
The first step was to try adding the "-uvm" option on the command line, so then I can add my uvm units to the environment. The problem is that I get an elaboration error just for adding the "-uvm" argument to the irun call:
tc_driver testc( |ncelab: *E,CUVMUR (/.../my_tb.sv,148|15): instance 'my_tb.testc' of design unit 'tc_driver' is unresolved in 'worklib.viking_digital_top_tb:sv'
What I'm I doing wrong? Is it possible to do this?
In reply to Frederico Laydner:
In reply to tpylant:
Thanks a lot for your help Tim.
You were right. I had an error in my scripts, omitting the tc_driver file when "-uvm" option was active. I Fixed it. Now I can instantiate and see both environments running together, the non-uvm systemC and the passive UVM SV.
I am just having a little problem with the end of simulation. The systemC environment finishes the simulation trough sc_stop() and the UVM environment is unable to run the report_phase after that.
The way I managed to add both environments to run together on incsim was: I created an uvm test which instatiates an environment with all agents configured to passive (monitors and collectors only). On the run_phase of this test I had to raise an objection, because it was finishing on time zero through UVM. Am I making it right?
class test_cov_only extends uvm_test... task run_phase(uvm_phase phase); `uvm_info(get_type_name(), "Starting test", UVM_MEDIUM) phase.raise_objection(this); //phase.drop_objection(this); // no objection drop to avoid end of test on time zero endtask: run_phase...endclass
I know I could probably edit my systemC stimulus routines to comunicate with the SV-UVM passive test environment. I'm trying to avoid that since I hope there is an easier way to accomplish this "sincronization" between the environments. If there is no other way, I will probably leave it like it is now (no uvm report_phase is ran). At least I'm getting the coverage I wanted...