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Is it possible to decalre Tasks in a seperate file (without module or class) and use the task in a program or module.
task.sv: File name
$display ("In task");
Inorder to accomodate above implementation what changes to be made in the code.
Thanks in advance.
Thanks & Regards,
i think u may have to import the module or package in which the program exists... import:: this enables u to use all the module properties.... (data types ,functions, tasks.. etc)
Hi,You can declare tasks (and functions) in a SystemVerilog package. The package contents can then be imported, one-by-one or with a wildcard, into any program or module. This is a cleaner solution than using Verilog `include. e.g.//simple_package.svpackage simple_package; task test(); $display("This is a test\n"); endtask // testendpackage // simple_package//simple_program.svprogram simple(); import simple_package::test; initial begin $display("Calling test.."); test(); endendprogram // simpleThe command "irun *.sv" generates the following output: Calling test..This is a testRegards,Dave