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I used Xilinx ISE to generate .vcd file for my design and then read it in RC 11.2 in order to estimate power consumption. I got the following report:
Asserted primary inputs in design : 99 (100.00%)
Total connected primary inputs in design : 99 (100.00%)
Asserted sequential outputs : 528 (99.25%)
Total connected sequential outputs : 532 (100.00%)
Total nets in design : 3857 (100.00%)
Nets asserted : 1899 (49.24%)
Constant nets : 3 (0.08)
Nets with no assertions : 1958 (50.76%)
Is 50.76% too high? I noticed that many nets in RC ended with _number like count_436. Is this the reason?
Seems like the Xilinx tools you are using is modifying the net names hence RC cannot annotate them. The good news is net annotation is not nearly as important since it is not what is conisdered a 'synthesis-invariant' point. In other words, tools are frequently not guaranteed to be able to keep or predict all net names. Furthermore, net activity will be recomputed by propagating the activity of the sequential outputs your successfully annotated. In fact, if all you care about is static power and not power/toggle vs timing, then recommendation would be to just do
write_tcf -boundary_only -hierarchical . . .
and use the TCF from that point since it will read faster and it will no longer have the nets in it.