Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I have a datapath module, after synthesize -to_generic, there are some CSA module has been added by RC, which naming is very ugly. Both in module name and instance name.
its RTL is :assign mout_int = smult(coeff,datain); where smult is a function.
its instance name is : \smult_30_22:mux_59_9_g1, I don't want "/" and ":" which is not accepted by STA tool. I can't find the option to change name. Besides re-write by design compiler, is there any option in RC I can use to replace them?
I also got ugly module name such as \csa_tree_smult_30_22:sub_62_34_group_325
thanks for the help!
Any reason you cannot use change_names to address whatever limitatios the downstream tools may have ?
In reply to grasshopper:
Thanks for the help. I did not find this command before you mentioned it.I search for lots of attributes and don't know there is a command for it.
But I am still curious if there is command/attribute such as "hdl_use_if_generate_prefix" which can constraint the tool "before" the elaboration.
In reply to tompy:
> apropo names
> apropo naming
should show you all attributes and commands witth such words in their names or their help strings. As per a specific attribute to control naming exclusively for functions, there is no such thing documented that I am aware of. If your STA does not support the current syntax for functions, or anything else for that mattter, why not use change_names and ensure that your output, whether from functions or anything else, is STA friendly? Seems like a more comprehensive solution to me
one more comment on naming attributes. Generally speaking, naming style use a default to increase "by name" compatibility with Formal tools (LEC, Formality, etc). The more you change the naming defaults without changing on the formal setup, the more likely you will see increases in runtime and potentially even aborts.